{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,13]],"date-time":"2024-04-13T04:29:35Z","timestamp":1712982575566},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,8,10]]},"DOI":"10.1587\/elex.19.20220281","type":"journal-article","created":{"date-parts":[[2022,6,29]],"date-time":"2022-06-29T22:09:41Z","timestamp":1656540581000},"page":"20220281-20220281","source":"Crossref","is-referenced-by-count":3,"title":["Low jitter design for quarter-rate CDR of 100Gb\/s PAM4 optical receiver"],"prefix":"10.1587","volume":"19","author":[{"given":"Sheng","family":"Xie","sequence":"first","affiliation":[{"name":"Tianjin Key Laboratory of Imaging and Sensing Micro-electronic Technology, School of Microelectronics, Tianjin University"}]},{"given":"Chengkui","family":"Jia","sequence":"additional","affiliation":[{"name":"Tianjin Key Laboratory of Imaging and Sensing Micro-electronic Technology, School of Microelectronics, Tianjin University"}]},{"given":"Luhong","family":"Mao","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University"}]},{"given":"Gaolei","family":"Zhou","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University"}]},{"given":"Naibo","family":"Zhang","sequence":"additional","affiliation":[{"name":"The 54th Research Institute, China Electronics Technology Group Corporation"}]},{"given":"Ruiliang","family":"Song","sequence":"additional","affiliation":[{"name":"The 54th Research Institute, China Electronics Technology Group Corporation"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Y. Krupnik, <i>et al.<\/i>: \u201c112-Gb\/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1077 (DOI: 10.1109\/JSSC.2019.2959511).","DOI":"10.1109\/JSSC.2019.2959511"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] W. Han, <i>et al.<\/i>: \u201cA 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210302 (DOI: 10.1587\/elex.18.20210302).","DOI":"10.1587\/elex.18.20210302"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] J. Lee, <i>et al.<\/i>: \u201cA 75-GHz phase-locked loop in 90-nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 1414 (DOI: 10.1109\/JSSC.2008.922719).","DOI":"10.1109\/JSSC.2008.922719"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S.S. Hajari and S. Sheikhaei: \u201cA novel quarter-rate binary phase detector with inherent de-multiplexer and majority voter,\u201d 2015 23rd Iranian Conference on Electrical Engineering (2008) 1144 (DOI: 10.1109\/IranianCEE.2015.7146385).","DOI":"10.1109\/IranianCEE.2015.7146385"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] G. Zhu, <i>et al.<\/i>: \u201cA low-power PAM4 receiver using 1\/4-rate sampling decoder with adaptive variable-gain rectification,\u201d 2017 IEEE Asian Solid-State Circuits Conference (2017) 81 (DOI: 10.1109\/ASSCC.2017.8240221).","DOI":"10.1109\/ASSCC.2017.8240221"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Z. Zhang, <i>et al.<\/i>: \u201cA 32-Gb\/s 0.46-pJ\/bit PAM4 CDR using a quarter-rate linear phase detector and a self-biased PLL-based multiphase clock generator,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2734 (DOI: 10.1109\/JSSC.2020.3005780).","DOI":"10.1109\/JSSC.2020.3005780"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Wang, <i>et al.<\/i>: \u201cA low jitter 50Gb\/s PAM4 CDR of receiver in 40nm CMOS technology,\u201d 2020 International Conference on Wireless Communications and Signal Processing (2020) 349 (DOI: 10.1109\/WCSP49889.2020.9299712).","DOI":"10.1109\/WCSP49889.2020.9299712"},{"key":"8","unstructured":"[8] IEEE.P802.3bs\/D3.5, \u201cDraft standard for Ethernet amendment 10: media access control parameters, physical layers and management parameters for 200Gb\/s and 400Gb\/s operation\u201d (2017) http:\/\/www. ieee802.org\/3\/bs\/"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] F. Lv, <i>et al.<\/i>: \u201cDesign of 56Gb\/s PAM4 wire-line receiver with ring VCO based CDR in a 65nm CMOS technology,\u201d 2017 IEEE 12th International Conference on ASIC (2017) 537 (DOI: 10.1109\/ASICON.2017.8252531).","DOI":"10.1109\/ASICON.2017.8252531"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Q. Liao, <i>et al.<\/i>: \u201cThe design techniques for high-speed PAM4 clock and data recovery,\u201d 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (2018) 142 (DOI: 10.1109\/CICTA.2018.8706109).","DOI":"10.1109\/CICTA.2018.8706109"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J. Lee, <i>et al.<\/i>: \u201cDesign and comparison of three 20-Gb\/s backplane transceivers for duobinary, PAM4, and NRZ Data,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 2120 (DOI: 10.1109\/JSSC.2008.2001934).","DOI":"10.1109\/JSSC.2008.2001934"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Lee, <i>et al.<\/i>: \u201c56Gb\/s PAM4 and NRZ SerDes transceivers in 40nm CMOS,\u201d 2015 Symposium on VLSI Circuits (2015) C118 (DOI: 10.1109\/VLSIC.2015.7231346).","DOI":"10.1109\/VLSIC.2015.7231346"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] X. Zhao, <i>et al.<\/i>: \u201cA 0.14-to-0.29-pJ\/bit 14-GBaud\/s trimodal (NRZ\/PAM-4\/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 89 (DOI: 10.1109\/TCSI.2020.3038865).","DOI":"10.1109\/TCSI.2020.3038865"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] X. Yangdong, <i>et al.<\/i>: \u201cA half-rate bang-bang clock and data recovery circuit for 56Gb\/s PAM4 receiver in 65nm CMOS,\u201d 2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) (2021) 28 (DOI: 10.1109\/ICICM54364.2021.9660336).","DOI":"10.1109\/ICICM54364.2021.9660336"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] N. Qi, <i>et al.<\/i>: \u201cA 51Gb\/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects,\u201d 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2017) 89 (DOI: 10.1109\/ASSCC.2017.8240223).","DOI":"10.1109\/ASSCC.2017.8240223"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Q. Liao, <i>et al.<\/i>: \u201cA dual-28Gb\/s digital-assisted distributed driver with CDR for optical-DAC PAM4 modulation in 40nm CMOS,\u201d 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2019) 219 (DOI: 10.1109\/RFIC.2019.8701783).","DOI":"10.1109\/RFIC.2019.8701783"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T.J. Ahn, <i>et al.<\/i>: \u201cA low-power CDR using dynamic CML latches and V\/I converter merged with XOR for half-rate linear phase detection,\u201d IEICE Electron. Express <b>11<\/b> (2014) 20140657 (DOI: 10.1587\/elex.11.20140657).","DOI":"10.1587\/elex.11.20140657"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Y.H. Zhang and X. Yang: \u201cA 36Gb\/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13\u00b5m BiCMOS technology,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200009 (DOI: 10.1587\/elex.17.20200009).","DOI":"10.1587\/elex.17.20200009"},{"key":"19","unstructured":"[19] K.K. Kyung, <i>et al.<\/i>: \u201cData dependent jitter (DDJ) characterization methodology,\u201d 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2005) 294 (DOI: 10.1109\/DFTVS.2005.25)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] T. Liang, <i>et al.<\/i>: \u201cMinimizing the jitter of duty cycle distortion correction technology based on cross point eye diagram correction,\u201d IEEE Access <b>7<\/b> (2019) 106238 (DOI: 10.1109\/ACCESS.2019.2931474).","DOI":"10.1109\/ACCESS.2019.2931474"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] N. Ou, <i>et al.<\/i>: \u201cJitter models for the design and test of Gbps-speed serial interconnects,\u201d IEEE Des. Test Comput. <b>21<\/b> (2004) 302 (DOI: 10.1109\/MDT.2004.34).","DOI":"10.1109\/MDT.2004.34"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] D.B. Leeson, <i>et al.<\/i>: \u201cA simple model of feedback oscillator noise spectrum,\u201d Proc. IEEE <b>54<\/b> (1966) 329 (DOI: 10.1109\/PROC.1966.4682).","DOI":"10.1109\/PROC.1966.4682"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] Y. Zhao and B. Razavi: \u201cA 19-GHz PLL with 20.3-fs Jitter,\u201d 2021 Symposium on VLSI Circuits (2021) 1 (DOI: 10.23919\/VLSICircuits52068.2021.9492419).","DOI":"10.23919\/VLSICircuits52068.2021.9492419"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] B. Razavi, <i>et al.<\/i>: \u201cJitter-power trade-offs in PLLs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 1381 (DOI: 10.1109\/TCSI.2021.3057580).","DOI":"10.1109\/TCSI.2021.3057580"},{"key":"25","unstructured":"[25] K.M. Ko, <i>et al.<\/i>: \u201cDesign of 20Gb\/s PAM4 transmitter with maximum transition elimination and transition compensation techniques,\u201d 18th International SoC Design Conference (2021) 405 (DOI: 10.1109\/ISOCC53507.2021.9613901)."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] G. Hou and B. Razavi: \u201cA 56-Gb\/s 8-mW PAM4 CDR\/DMUX with high jitter tolerance,\u201d IEEE J. Solid-State Circuits (2022) 1 (DOI: 10.1109\/JSSC.2022.3153695).","DOI":"10.1109\/JSSC.2022.3153695"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Xie, <i>et al.<\/i>: \u201cAn energy- and area-efficient limiting amplifier with interleaving feedback for 25Gb\/s optical receiver,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210112 (DOI: 10.1587\/elex.18.20210112).","DOI":"10.1587\/elex.18.20210112"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Lee, <i>et al.<\/i>: \u201cAnalysis and modeling of bang-bang clock and data recovery circuits,\u201d IEEE J. Solid-State Circuits <b>39<\/b> (2004) 1571 (DOI: 10.1109\/JSSC.2004.831600).","DOI":"10.1109\/JSSC.2004.831600"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] J. Lee and B. Razavi: \u201cA 40Gb\/s clock and data recovery circuit in 0.18\u00b5m CMOS technology,\u201d International Solid-State Circuits Conference (2003) 242 (DOI: 10.1109\/ISSCC.2003.1234285).","DOI":"10.1109\/JSSC.2003.818566"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Y. Dong, <i>et al.<\/i>: \u201cA bidirectional nonlinearly coupled QVCO with passive phase interpolation for multiphase signals generation,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 1480 (DOI: 10.1109\/TVLSI.2021.3077613).","DOI":"10.1109\/TVLSI.2021.3077613"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/15\/19_19.20220281\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,13]],"date-time":"2022-08-13T03:14:52Z","timestamp":1660360492000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/15\/19_19.20220281\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,10]]},"references-count":30,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220281","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,8,10]]},"article-number":"19.20220281"}}