{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T05:02:03Z","timestamp":1744434123558},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"23","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,12,10]]},"DOI":"10.1587\/elex.19.20220351","type":"journal-article","created":{"date-parts":[[2022,11,7]],"date-time":"2022-11-07T22:15:56Z","timestamp":1667859356000},"page":"20220351-20220351","source":"Crossref","is-referenced-by-count":2,"title":["A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture"],"prefix":"10.1587","volume":"19","author":[{"given":"Jialu","family":"Yin","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Jia","family":"Yuan","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences"}]},{"given":"Zhi","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Shushan","family":"Qiao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. 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Chiu, <i>et al.<\/i>: \u201c40nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 2578 (DOI: 10.1109\/TCSI.2014.2332267).","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] V. Sharma, <i>et al.<\/i>: \u201cHalf-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications,\u201d AEU-International Journal of Electronics and Communications <b>104<\/b> (2019) 10 (DOI: 10.1016\/j.aeue.2019.02.018).","DOI":"10.1016\/j.aeue.2019.02.018"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] J.B. Zhang, <i>et al.<\/i>: \u201cA disturb-free 10T SRAM cell with high read stability and write ability for ultra-low voltage operations,\u201d IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2018) 305 (DOI: 10.1109\/APCCAS.2018.8605599).","DOI":"10.1109\/APCCAS.2018.8605599"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S. Ahmad, <i>et al.<\/i>: \u201cPseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications,\u201d AEU-International Journal of Electronics and Communications <b>83<\/b> (2016) 366 (DOI: 10.1016\/j.aeue.2017.09.022).","DOI":"10.1016\/j.aeue.2017.09.022"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] M.S.M. Siddiqui, <i>et al.<\/i>: \u201cA 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 1707 (DOI: 10.1109\/TVLSI.2021.3102675).","DOI":"10.1109\/TVLSI.2021.3102675"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] H. Fujiwara, <i>et al.<\/i>: \u201cA 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb standard-cell-based two-port register file with a 16T bitcell with no half-selection issue,\u201d IEEE International Solid-State Circuits Conference-(ISSCC) (2021) 64 (DOI: 10.1109\/ISSCC42613.2021.9366000).","DOI":"10.1109\/ISSCC42613.2021.9366000"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H. Qiu, <i>et al.<\/i>: \u201cComparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells,\u201d Jpn. J. Appl. Phys. <b>54<\/b> (2015) 04DC09 (DOI: 10.7567\/JJAP.54.04DC09).","DOI":"10.7567\/JJAP.54.04DC09"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] D.-B. Kong, <i>et al.<\/i>: \u201cA robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180758 (DOI: 10.1587\/elex.15.20180758).","DOI":"10.1587\/elex.15.20180758"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] A. Islam and M. Hasan: \u201cLeakage characterization of 10T SRAM cell,\u201d IEEE Trans. Electron Devices <b>59<\/b> (2012) 631 (DOI: 10.1109\/TED.2011.2181387).","DOI":"10.1109\/TED.2011.2181387"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/23\/19_19.20220351\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,10]],"date-time":"2024-05-10T04:28:12Z","timestamp":1715315292000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/23\/19_19.20220351\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,10]]},"references-count":31,"journal-issue":{"issue":"23","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220351","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12,10]]},"article-number":"19.20220351"}}