{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T04:09:56Z","timestamp":1751083796660},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"22","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,11,25]]},"DOI":"10.1587\/elex.19.20220429","type":"journal-article","created":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T22:18:10Z","timestamp":1666045090000},"page":"20220429-20220429","source":"Crossref","is-referenced-by-count":7,"title":["6.25-10Gb\/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18\u00b5m CMOS"],"prefix":"10.1587","volume":"19","author":[{"given":"Haoran","family":"Sun","sequence":"first","affiliation":[{"name":"College of Communication and Electronic Engineering, Jishou University"}]},{"given":"Yinhang","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Communication and Electronic Engineering, Jishou University"}]},{"given":"Xi","family":"Yang","sequence":"additional","affiliation":[{"name":"College of Communication and Electronic Engineering, Jishou University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] M. Zhang, <i>et al<\/i>.: \u201cA 24Gb\/s high speed adaptive combined equalizer for backplane communication,\u201d Acta Electronica Sinica <b>45<\/b> (2017) 1608 (DOI: 10.3969\/j.issn.0372-2112.2017.07.009)."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Yuan, <i>et al<\/i>.: \u201cA 70mW 25Gb\/s quarter-rate SerDes transmitter and receiver chipset with 40dB of equalization in 65nm CMOS technology,\u201d IEEE Trans. Circuits Syst I, Reg. Papers. <b>63<\/b> (2016) 939 (DOI: 10.1109\/TCSI.2016.2555250).","DOI":"10.1109\/TCSI.2016.2555250"},{"key":"3","unstructured":"[3] P. Manh Ha, <i>et al<\/i>.: \u201cAn adaptive continuous-time linear equalizer using sampled data edge counting,\u201d International Symposium on Communications and Information Technologies (ISCIT) (2019) 192 (DOI: 10.1109\/ISCIT.2019.8905130)."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Chen, <i>et al<\/i>.: \u201cA 0.002-mm 6.4-mW 10-Gb\/s full-rate direct DFE receiver with 59.6% horizontal eye opening under 23.3-dB channel loss at Nyquist frequency,\u201d IEEE Trans. Microw. Theory Techn. <b>62<\/b> (2017) 3107 (DOI: 10.1109\/TMTT.2014.2360697).","DOI":"10.1109\/TMTT.2014.2360697"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A. Atharav and B. Razavi: \u201cA 56Gb\/s 50mW NRZ receiver in 28nm CMOS,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 54 (DOI: 10.1109\/JSSC.2021.3109032).","DOI":"10.1109\/JSSC.2021.3109032"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Turker, <i>et al<\/i>.: \u201cDesign techniques for 32.75Gb\/s and 56Gb\/s wireline transceivers in 16nm FinFET,\u201d IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) (2017) 1 (DOI: 10.1109\/CSICS.2017.8240462).","DOI":"10.1109\/CSICS.2017.8240462"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] D. Menin, <i>et al<\/i>.: \u201cDesign and simulation of a 12Gb\/s transceiver with 8-Tap FFE, offset-compensated samplers and fully adaptive 1-Tap speculative\/3-Tap DFE and sampling phase for MIPI A-PHY applications,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 1369 (DOI: 10.1109\/TCSII.2019.2926152).","DOI":"10.1109\/TCSII.2019.2926152"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] A. Balachandran, <i>et al<\/i>.: \u201cA 0.013-mm2 0.53-mW\/Gb\/s 32-Gb\/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 599 (DOI: 10.1109\/TVLSI.2017.2771429).","DOI":"10.1109\/TVLSI.2017.2771429"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] H. Li, <i>et al<\/i>.: \u201cA 100-Gb\/s PAM-4 optical receiver with 2-tap FFE and 2-tap direct-feedback DFE in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 44 (DOI: 10.1109\/JSSC.2021.3110088).","DOI":"10.1109\/JSSC.2021.3110088"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] A. Balachandran, <i>et al<\/i>.: \u201cA 32-Gb\/s 3.53-mW\/Gb\/s adaptive receiver AFE employing a hybrid CTLE, edge-DFE and merged Data-DFE\/CDR in 65-nm CMOS,\u201d IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2019) 221 (DOI: 10.1109\/APCCAS47518.2019.8953146).","DOI":"10.1109\/APCCAS47518.2019.8953146"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] H. Chen, <i>et al<\/i>.: \u201cAn 11.05mW\/Gbps quad-channel 1.25-10.3125Gbps serial transceiver with a 2-Tap adaptive DFE and a 3-Tap transmit FFE in 40nm CMOS,\u201d IEEE Access <b>9<\/b> (2021) 70856 (DOI: 10.1109\/ACCESS.2021.3078844).","DOI":"10.1109\/ACCESS.2021.3078844"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Han, <i>et al<\/i>.: \u201cDesign techniques for a 60Gb\/s 173mW wireline receiver frontend in 65nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 871 (DOI: 10.1109\/JSSC.2016.2519389).","DOI":"10.1109\/JSSC.2016.2519389"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y. Lin, <i>et al<\/i>.: \u201cA 10-Gb\/s eye-opening monitor circuit for receiver equalizer adaptations in 65-nm CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>28<\/b> (2019) 23 (DOI: 10.1109\/TVLSI.2019.2935305).","DOI":"10.1109\/TVLSI.2019.2935305"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Tu, <i>et al<\/i>.: \u201cA 5-Gb\/s serial-link redriver with adaptive equalizer and transmitter swing enhancement,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>61<\/b> (2014) 1001 (DOI: 10.1109\/TCSI.2013.2283675).","DOI":"10.1109\/TCSI.2013.2283675"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J. Lee: \u201cA 20Gb\/s adaptive equalizer in 0.13\u00b5m CMOS technology,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 2058 (DOI: 10.1109\/JSSC.2006.880629).","DOI":"10.1109\/JSSC.2006.880629"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] C. Chen, <i>et al<\/i>.: \u201c5-20Gbit\/s adaptive CTLE with spectrum balancing method,\u201d Electronics Letters <b>54<\/b> (2018) 274 (DOI: 10.1049\/el.2017.4225).","DOI":"10.1049\/el.2017.4225"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] J.F. Bulzacchelli, <i>et al<\/i>.: \u201cEqualization for electrical links: current design techniques and future directions,\u201d IEEE Solid-State Circuits Mag. <b>7<\/b> (2015) 23 (DOI: 10.1109\/MSSC.2015.2475996).","DOI":"10.1109\/MSSC.2015.2475996"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] S. Ibrahim, <i>et al<\/i>.: \u201cLow-power CMOS equalizer design for 20-Gb\/s systems,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2020) 1321 (DOI: 10.1109\/JSSC.2011.2134450).","DOI":"10.1109\/JSSC.2011.2134450"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] B. Lim, <i>et al<\/i>.: \u201cA 12.4-mW 4.5-Gb\/s receiver with majority-voting 1-tap speculative DFE in 0.13-\u00b5m CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>60<\/b> (2013) 867 (DOI: 10.1109\/TCSII.2013.2281946).","DOI":"10.1109\/TCSII.2013.2281946"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Y. Zhang, <i>et al<\/i>.: \u201cA 36Gb\/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13\u00b5m BiCMOS technology,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200009 (DOI: 10.1587\/elex.17.20200009).","DOI":"10.1587\/elex.17.20200009"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y.L. Lee and S.J. Chang: \u201cA 10-fJ\/bit\/dB half-rate equalizer with charge-average switched-capacitor summation technique,\u201d International Symposium on Next-Generation Electronics (ISNE), (2016) 1 (DOI: 10.1109\/ISNE.2016.7543355).","DOI":"10.1109\/ISNE.2016.7543355"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] G. Jeon and Y.-B. Kim: \u201cA quarter-rate 3-tap DFE for 4Gbps data rate with switched-capacitors based 1st speculative tap,\u201d International SoC Design Conference (2017) 244 (DOI: 10.1109\/ISOCC.2017.8368875).","DOI":"10.1109\/ISOCC.2017.8368875"},{"key":"23","unstructured":"[23] T. Manvel Grigoryan, <i>et al<\/i>.: \u201cA 50Gb\/s serial link receiver with inductive peaking CTLE and 1-tap loop-unrolled DFE in 22nm FDSOI CMOS,\u201d IEEE MTT-S International Wireless Symposium (IWS) (2020) 374 (DOI: 10.1109\/IWS49314.2020.9360200)."},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] G. Talluri and M.S. Baghini: \u201cA closed loop inductorless equalizer with a modified analysis of power comparator behaviour,\u201d Journal of Circuit Theory and Applications <b>48<\/b> (2020) 777 (DOI: doi.org\/10.1002\/cta.2749).","DOI":"10.1002\/cta.2749"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] W. Choi, <i>et al<\/i>.: \u201cA power-and area-efficient DFE receiver with tap coefficient-rotating summer for IoT applications,\u201d IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) (2021) 1 (DOI: 10.1109\/ICCE-Asia53811.2021.9641947).","DOI":"10.1109\/ICCE-Asia53811.2021.9641947"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] M. Kim, <i>et al<\/i>.: \u201cA 24-mW 28-Gb\/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2015) 1610 (DOI: 10.1109\/ISCAS.2015.7168957).","DOI":"10.1109\/ISCAS.2015.7168957"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] A. Ismail, <i>et al<\/i>.: \u201cA 8Gbps 0.67mW 1 tap current integrating DFE in 40nm CMOS,\u201d IEEE 57th International Midwest Symposium on Circuits and Systems (2014) 81 (DOI: 10.1109\/MWSCAS.2014.6908357).","DOI":"10.1109\/MWSCAS.2014.6908357"},{"key":"28","unstructured":"[28] G. Talluri, <i>et al<\/i>.: \u201cAn area efficient 4Gb\/s half-rate 3-tap DFE with current-integrating summer for data correction,\u201d IEEE 25th North Atlantic Test Workshop (NATW) (2016) 7 (DOI: 10.1109\/NATW.2016.11)."},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] P. Chandrika Kondeti, <i>et al<\/i>.: \u201cCurrent-integrating summer for DFE receiver with low common mode variation,\u201d Microelectronics Journal <b>123<\/b> (2022) 1 (DOI: 10.1016\/j.mejo.2022.105408).","DOI":"10.1016\/j.mejo.2022.105408"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] C. Cai, <i>et al<\/i>.: \u201cA 1.25-12.5Gbps adaptive CTLE with asynchronous statistic eye-opening monitor,\u201d Journal of Electrical and Computer Engineering <b>2018<\/b> (2018) 3095950 (DOI: 10.1155\/2018\/3095950).","DOI":"10.1155\/2018\/3095950"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] Y.-H. Kim, <i>et al<\/i>.: \u201cA 21-Gbit\/s 1.63-pJ\/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 789 (DOI: 10.1109\/TCSI.2017.2695612).","DOI":"10.1109\/TVLSI.2015.2418579"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] Y. Tu, <i>et al<\/i>.: \u201cA power-saving adaptive equalizer with a digital-controlled self-slope detection,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers, <b>65<\/b> (2018) 2097 (DOI: 10.1109\/TCSI.2017.2781302).","DOI":"10.1109\/TCSI.2017.2781302"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/22\/19_19.20220429\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,26]],"date-time":"2022-11-26T04:23:08Z","timestamp":1669436588000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/22\/19_19.20220429\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,25]]},"references-count":32,"journal-issue":{"issue":"22","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220429","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,11,25]]},"article-number":"19.20220429"}}