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Kimura, <i>et al<\/i>.: \u201cA 28Gb\/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision feedback equalizer in 28nm CMOS,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 3091 (DOI: 10.1109\/JSSC.2014.2349974).","DOI":"10.1109\/ISSCC.2014.6757327"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Guo, <i>et al<\/i>.: \u201cA low-voltage lowpower 25Gb\/s clock and data recovery with equalizer in 65nm CMOS,\u201d IEEE RFIC Symp. (RFIC) (2015) 307 (DOI: 10.1109\/RFIC.2015.7337766).","DOI":"10.1109\/RFIC.2015.7337766"},{"key":"3","unstructured":"[3] P. Wang, <i>et al<\/i>.: \u201cA 40Gb\/s quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS,\u201d 2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) (2014) 1 (DOI: 10.1109\/EDSSC.2014.7061137)."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Krupnik, <i>et al<\/i>.: \u201c112-Gb\/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1077 (DOI: 10.1109\/JSSC.2019.2959511).","DOI":"10.1109\/JSSC.2019.2959511"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] K. Park, <i>et al<\/i>.: \u201cA 30Gb\/s all-digital CDR with a phase error compensator,\u201d 2020 International Conference on Electronics, Information, and Communication (ICEIC) (2020) 1 (DOI: 10.1109\/ICEIC49074.2020.9051017).","DOI":"10.1109\/ICEIC49074.2020.9051017"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Noguchi, <i>et al<\/i>.: \u201cA 25-Gb\/s low-power clock and data recovery with an active-stabilizing CML-CMOS conversion,\u201d 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2018) 49 (DOI: 10.1109\/ICECS.2018.8617976).","DOI":"10.1109\/ICECS.2018.8617976"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] D. Wang, <i>et al<\/i>.: \u201cA 28Gbps reference-less VCO based CDR with separate proportional path technology in 65nm CMOS,\u201d 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) (2017) 1 (DOI: 10.1109\/EDSSC.2017.8126550).","DOI":"10.1109\/EDSSC.2017.8126550"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J. Im, <i>et al<\/i>.: \u201cA 0.5-28GB\/s wireline tranceiver with 15-tap DFE and fast-locking digital CDR in 7NM FinFET,\u201d 2018 IEEE Symposium on VLSI Circuits (VLSIC) (2018) 145 (DOI: 10.1109\/VLSIC.2018.8502275).","DOI":"10.1109\/VLSIC.2018.8502275"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] S. Guo, <i>et al<\/i>.: \u201cA 16\/32Gb\/s NRZ\/PAM4 receiver with dual-loop CDR and threshold voltage calibration,\u201d 2019 IEEE 13th International Conference on ASIC (ASICON) (2019) 1 (DOI: 10.1109\/ASICON47005.2019.8983675).","DOI":"10.1109\/ASICON47005.2019.8983675"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] H. Hwang and J. Kim: \u201cA low-power 20Gbps multi-phase MDLL-based digital CDR with receiver equalization,\u201d 2019 International SoC Design Conference (ISOCC) (2019) 42 (DOI: 10.1109\/ISOCC47750.2019.9078536).","DOI":"10.1109\/ISOCC47750.2019.9078536"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S.-H. Chu, <i>et al<\/i>.: \u201cA 22 to 26.5Gb\/s optical receiver with all-digital clock and data recovery in a 65nm CMOS process,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2603 (DOI: 10.1109\/JSSC.2015.2465843).","DOI":"10.1109\/JSSC.2015.2465843"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] K. Park, <i>et al<\/i>.: \u201cA 4-20-Gb\/s 1.87-pJ\/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 1597 (DOI: 10.1109\/JSSC.2020.3030816).","DOI":"10.1109\/JSSC.2020.3030816"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] J. Lee, <i>et al<\/i>.: \u201cA 2.44-pJ\/b 1.62-10-Gb\/s receiver for next generation video interface equalizing 23-dB loss with adaptive 2-tap data DFE and 1-tap edge DFE,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1295 (DOI: 10.1109\/TCSII.2018.2846677).","DOI":"10.1109\/TCSII.2018.2846677"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] G. Shu, <i>et al<\/i>.: \u201cA 4-to-10.5Gb\/s continuous-rate digital clock and data recovery with automatic frequency acquisition,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 428 (DOI: 10.1109\/JSSC.2015.2497963).","DOI":"10.1109\/JSSC.2015.2497963"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Huang, <i>et al<\/i>.: \u201cAn 8.2Gb\/s-to-10.3Gb\/s full-rate linear referenceless CDR without frequency detector in 0.18\u00b5m CMOS,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2048 (DOI: 10.1109\/JSSC.2015.2427332).","DOI":"10.1109\/JSSC.2015.2427332"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] J. Liang, <i>et al<\/i>.: \u201c6.7 A 28Gb\/s digital CDR with adaptive loop gain for optimum jitter tolerance,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) 122 (DOI: 10.1109\/ISSCC.2017.7870291).","DOI":"10.1109\/ISSCC.2017.7870291"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] B. Terlemez and B. Dundar: \u201cA novel half-rate dual-response phase detector implementation for a 25-28.3Gb\/s clock and data recovery circuit,\u201d 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2018) 45 (DOI: 10.1109\/ICECS.2018.8618026).","DOI":"10.1109\/ICECS.2018.8618026"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M. Hsieh and G. Sobelman: \u201cArchitectures for multi-gigabit wire-linked clock and data recovery,\u201d IEEE Circuits Syst. Mag. <b>8<\/b> (2008) 45 (DOI: 10.1109\/MCAS.2008.930152).","DOI":"10.1109\/MCAS.2008.930152"},{"key":"19","unstructured":"[19] X. Chen and Y. Chen: \u201cA 9.95-11.5Gb\/s full rate CDR with jitter attenuation PLL in 65-nm CMOS technology,\u201d 2011 IEEE 13th International Conference on Communication Technology (2011) 273 (DOI: 10.1109\/ICCT.2011.6157877)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Z. Wang, <i>et al<\/i>.: \u201cA 25Gbps, 2x-oversampling CDR using a zero-crossing linearizing phase detector,\u201d 2014 IEEE Radio Frequency Integrated Circuits Symposium (2014) 271 (DOI: 10.1109\/RFIC.2014.6851717).","DOI":"10.1109\/RFIC.2014.6851717"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C. Yu, <i>et al<\/i>.: \u201cA 6.5-12.5-Gb\/s half-rate single-loop all-digital referenceless CDR in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2831 (DOI: 10.1109\/JSSC.2020.3005750).","DOI":"10.1109\/JSSC.2020.3005750"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] X. Yi, <i>et al<\/i>.: \u201cA 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 347 (DOI: 10.1109\/JSSC.2013.2293021).","DOI":"10.1109\/JSSC.2013.2293021"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] A. Rofougaran, <i>et al<\/i>.: \u201cA single-chip 900-MHz spread-spectrum wireless transceiver in 1-\u00b5\/m CMOS. I. Architecture and transmitter design,\u201d IEEE J. Solid-State Circuits <b>33<\/b> (1998) 515 (DOI: 10.1109\/4.663557).","DOI":"10.1109\/4.663557"},{"key":"24","unstructured":"[24] T. Liu: \u201cA 6.5GHz monolithic CMOS voltage-controlled oscillator,\u201d 1999 IEEE ISSCC Dig. Tech Papers (1999) 404 (DOI: 10.1109\/ISSCC.1999.759323)."},{"key":"25","unstructured":"[25] R. Duncan, <i>et al<\/i>.: \u201cA 1GHz quadrature sinusoidal oscillator,\u201d Proc. IEEE 1995 Custom Integrated Circuits Conference (CICC) (1995) 91 (DOI: 10.1109\/CICC.1995.518143)."},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. van der Tang, <i>et al<\/i>.: \u201cAnalysis and design of an optimally coupled 5-GHz quadrature LC oscillator,\u201d IEEE J. Solid-State Circuits <b>37<\/b> (2002) 657 (DOI: 10.1109\/4.997861).","DOI":"10.1109\/4.997861"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Li, <i>et al<\/i>.: \u201cA 10-GHz CMOS quadrature LC-VCO for multirate optical applications,\u201d IEEE J. SolidState Circuits <b>38<\/b> (2003) 1626 (DOI: 10.1109\/JSSC.2003.817258).","DOI":"10.1109\/JSSC.2003.817258"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Lee and M. Liu: \u201cA 20-Gb\/s burst-mode clock and data recovery circuit using injection-locking technique,\u201d IEEE J. Solid State Circuits <b>43<\/b> (2008) 619 (DOI: 10.1109\/JSSC.2007.916598).","DOI":"10.1109\/JSSC.2007.916598"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] S. Guo, <i>et al<\/i>.: \u201cA low-voltage low-power 25Gb\/s clock and data recovery with equalizer in 65nm CMOS,\u201d 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2015) 307 (DOI: 10.1109\/RFIC.2015.7337766).","DOI":"10.1109\/RFIC.2015.7337766"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] J. Liang, <i>et al<\/i>.: \u201cOn-chip jitter measurement using jitter injection in a 28Gb\/s PI-based CDR,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 750 (DOI: 10.1109\/JSSC.2017.2776307).","DOI":"10.1109\/JSSC.2017.2776307"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] H. Hwang and J. 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