{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T15:44:57Z","timestamp":1764603897163},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"24","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2022,12,25]]},"DOI":"10.1587\/elex.19.20220440","type":"journal-article","created":{"date-parts":[[2022,10,31]],"date-time":"2022-10-31T22:10:36Z","timestamp":1667254236000},"page":"20220440-20220440","source":"Crossref","is-referenced-by-count":2,"title":["Adaptive image recognition circuit based on CMOS-based memristor"],"prefix":"10.1587","volume":"19","author":[{"given":"Sheng","family":"Xie","sequence":"first","affiliation":[{"name":"Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Micrioelectronics, Tianjin University"}]},{"given":"Jinhao","family":"Gong","sequence":"additional","affiliation":[{"name":"Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Micrioelectronics, Tianjin University"}]},{"given":"Xurui","family":"Mao","sequence":"additional","affiliation":[{"name":"Institute of Semiconductors, Chinese Academy of Science"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Z. 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