{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,5,11]],"date-time":"2024-05-11T00:13:25Z","timestamp":1715386405468},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2023,6,10]]},"DOI":"10.1587\/elex.20.20230113","type":"journal-article","created":{"date-parts":[[2023,4,17]],"date-time":"2023-04-17T22:12:44Z","timestamp":1681769564000},"page":"20230113-20230113","source":"Crossref","is-referenced-by-count":0,"title":["FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme"],"prefix":"10.1587","volume":"20","author":[{"given":"Bo","family":"Zhang","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Qi","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Xiaolei","family":"Yu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Qianhui","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Jing","family":"He","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Xianliang","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Qianqi","family":"Zhao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Xuhong","family":"Qiang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Zongliang","family":"Huo","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]},{"given":"Tianchun","family":"Ye","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"The University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] G. 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Syst. <b>32<\/b> (2021) 1437 (DOI: 10.1109\/TPDS.2021.3052028).","DOI":"10.1109\/TPDS.2021.3052028"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/11\/20_20.20230113\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,10]],"date-time":"2024-05-10T04:28:38Z","timestamp":1715315318000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/11\/20_20.20230113\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,10]]},"references-count":32,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.20.20230113","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6,10]]},"article-number":"20.20230113"}}