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Mao, <i>et al<\/i>.: \u201cA survey on mobile edge computing: the communication perspective,\u201d IEEE Commun. Surveys Tuts. <b>19<\/b> (2017) 2322 (DOI: 10.1109\/COMST.2017.2745201).","DOI":"10.1109\/COMST.2017.2745201"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] E.B. Hansen and S. B\u00f8gh: \u201cArtificial intelligence and internet of things in small and medium-sized enterprises: A survey,\u201d Journal of Manufacturing Systems <b>58<\/b>(2021) 362 (DOI: 10.1016\/j.jmsy.2020.08.009).","DOI":"10.1016\/j.jmsy.2020.08.009"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] L. Chettri and R. Bera: \u201cA comprehensive survey on internet of things (IoT) toward 5G wireless systems,\u201d IEEE Internet Things J. <b>7<\/b> (2020) 16 (DOI: 10.1109\/JIOT.2019.2948888).","DOI":"10.1109\/JIOT.2019.2948888"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Stoyanova, <i>et al<\/i>.: \u201cA survey on the internet of things (IoT) forensics: challenges, approaches, and open issues,\u201d IEEE Commun. Surveys Tuts. <b>22<\/b> (2020) 1191 (DOI: 10.1109\/COMST.2019.2962586).","DOI":"10.1109\/COMST.2019.2962586"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] F. Pereira, <i>et al<\/i>.: \u201cChallenges in resource-constrained IoT devices: energy and communication as critical success factors for future IoT deployment,\u201d Sensors <b>20<\/b> (2020) 6420 (DOI: 10.3390\/s20226420).","DOI":"10.3390\/s20226420"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] K.A. Bowman, <i>et al<\/i>.: \u201cEnergy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 49 (DOI: 10.1109\/JSSC.2008.2007148).","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] B. Zhai, <i>et al<\/i>.: \u201cAnalysis and mitigation of variability in subthreshold design,\u201d Proc. 2005 International Symposium on Low Power Electronics and Design 2005 (ISLPED\u201905) (2005) 20 (DOI: 10.1109\/LPE.2005.195479).","DOI":"10.1109\/LPE.2005.195479"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] K. Bowman, <i>et al<\/i>.: \u201cCircuit techniques for dynamic variation tolerance,\u201d 2009 46th ACM\/IEEE Design Automation Conference (2009) 4 (DOI: 10.1145\/1629911.1629915).","DOI":"10.1145\/1629911.1629915"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] U.R. Karpuzcu, <i>et al<\/i>.: \u201cCoping with parametric variation at near-threshold voltages,\u201d IEEE Micro <b>33<\/b> (2013) 6 (DOI: 10.1109\/MM.2013.71).","DOI":"10.1109\/MM.2013.71"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] P. Pillai and K.G. Shin: \u201cReal-time dynamic voltage scaling for low-power embedded operating systems,\u201d Proc. eighteenth ACM symposium on Operating systems principles (SOSP\u201901) (2001) 89 (DOI: 10.1145\/502034.502044).","DOI":"10.1145\/502034.502044"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M. Elgebaly and M. Sachdev: \u201cVariation-aware adaptive voltage scaling system,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>15<\/b> (2007) 560 (DOI: 10.1109\/TVLSI.2007.896909).","DOI":"10.1109\/TVLSI.2007.896909"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Tschanz, <i>et al<\/i>.: \u201cAdaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging,\u201d 2007 IEEE International Solid-State Circuits Conference Dig. Tech. Papers (2007) 292 (DOI: 10.1109\/ISSCC.2007.373409).","DOI":"10.1109\/ISSCC.2007.373409"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S. Das, <i>et al<\/i>.: \u201cAddressing design margins through error-tolerant circuits,\u201d 2009 46th ACM\/IEEE Design Automation Conference (2009) 11 (DOI: 10.1145\/1629911.1629917).","DOI":"10.1145\/1629911.1629917"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] W.-J. Tsou, <i>et al<\/i>.: \u201c20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) 338 (DOI: 10.1109\/ISSCC.2017.7870399).","DOI":"10.1109\/ISSCC.2017.7870399"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J. Lee, <i>et al<\/i>.: \u201cA self-tuning IoT processor using leakage-ratio measurement for energy-optimal operation,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 87 (DOI: 10.1109\/JSSC.2019.2939890).","DOI":"10.1109\/JSSC.2019.2939890"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] T. Kuroda, <i>et al<\/i>.: \u201cVariable supply-voltage scheme for low-power high-speed CMOS digital design,\u201d IEEE J. Solid-State Circuits <b>33<\/b> (1998) 454 (DOI: 10.1109\/4.661211).","DOI":"10.1109\/4.661211"},{"key":"17","unstructured":"[17] J. Tschanz, <i>et al<\/i>.: \u201cTunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance,\u201d 2009 Symposium on VLSI Circuits (2009) 112."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] K.A. Bowman: \u201cAdaptive and resilient circuits: a tutorial on improving processor performance, energy efficiency, and yield via dynamic variation,\u201d IEEE Solid-State Circuits Mag. <b>10<\/b> (2018) 16 (DOI: 10.1109\/MSSC.2018.2844601).","DOI":"10.1109\/MSSC.2018.2844601"},{"key":"19","unstructured":"[19] D. Ernst, <i>et al<\/i>.: \u201cRazor: a low-power pipeline based on circuit-level timing speculation,\u201d Proc. 36th Annual IEEE\/ACM International Symposium on Microarchitecture 2003 (MICRO-36) (2003) 7 (DOI: 10.1109\/MICRO.2003.1253179)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] S. Das, <i>et al<\/i>.: \u201cRazorII: in situ error detection and correction for PVT and SER tolerance,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 32 (DOI: 10.1109\/JSSC.2008.2007145).","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Fojtik, <i>et al<\/i>.: \u201cBubble razor: eliminating timing margins in an ARM cortex-M3 processor in 45nm CMOS using architecturally independent error detection and correction,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 66 (DOI: 10.1109\/JSSC.2012.2220912).","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] I. Kwon, <i>et al<\/i>.: , \u201cRazor-lite: a light-weight register for error detection by observing virtual supply rails,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2054 (DOI: 10.1109\/JSSC.2014.2328658).","DOI":"10.1109\/JSSC.2014.2328658"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] S. Kim and M. Seok: \u201cVariation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1478 (DOI: 10.1109\/JSSC.2015.2418713).","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] J.-S. Wang and S.-N. Wei: \u201cProcess\/voltage\/temperature-variation-aware design and comparative study of transition-detector-based error-detecting latches for timing-error-resilient pipelined systems,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>25<\/b> (2017) 2893 (DOI: 10.1109\/TVLSI.2017.2723020).","DOI":"10.1109\/TVLSI.2017.2723020"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] Y. Zhang, <i>et al<\/i>.: \u201ciRazor: current-based error detection and correction scheme for PVT variation in 40-nm ARM cortex-R4 processor,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 619 (DOI: 10.1109\/JSSC.2017.2749423).","DOI":"10.1109\/JSSC.2017.2749423"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] H. Reyserhove and W. Dehaene: \u201cMargin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 2101 (DOI: 10.1109\/JSSC.2018.2821121).","DOI":"10.1109\/JSSC.2018.2821121"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] C.-Y. Hong and T.-T. Liu: \u201cA variation-resilient microprocessor with a two-level timing error detection and correction system in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2285 (DOI: 10.1109\/JSSC.2019.2951692).","DOI":"10.1109\/JSSC.2019.2951692"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] X. Shang, <i>et al<\/i>.: \u201cA wide-voltage-range transition-detector with in-situ timing-error detection and correction based on pulsed-latch design in 28nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 3933 (DOI: 10.1109\/TCSI.2020.3023157).","DOI":"10.1109\/TCSI.2020.3023157"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] W. Shan, <i>et al<\/i>.: \u201cTG-SPP: a one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1422 (DOI: 10.1109\/JSSC.2019.2948164).","DOI":"10.1109\/JSSC.2019.2948164"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] J. Liu, <i>et al<\/i>.: \u201cA dynamic voltage scaling circuit design based on critical path replica and time warning techniques,\u201d IEICE Electron. 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