{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,5,14]],"date-time":"2024-05-14T00:25:09Z","timestamp":1715646309700},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"16","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2023,8,25]]},"DOI":"10.1587\/elex.20.20230243","type":"journal-article","created":{"date-parts":[[2023,6,28]],"date-time":"2023-06-28T22:14:46Z","timestamp":1687990486000},"page":"20230243-20230243","source":"Crossref","is-referenced-by-count":0,"title":["A CJ-LMS hybrid calibration algorithm in SAR ADC"],"prefix":"10.1587","volume":"20","author":[{"given":"Yu","family":"Zhang","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"},{"name":"CASEMIC Electronics Technology Co. Ltd"}]},{"given":"Yilin","family":"Pu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"CASEMIC Electronics Technology Co. Ltd"}]},{"given":"Bin","family":"Wu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"CASEMIC Electronics Technology Co. Ltd"}]},{"given":"Haoyu","family":"Shen","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"},{"name":"CASEMIC Electronics Technology Co. Ltd"}]},{"given":"Tianchun","family":"Ye","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] C.C. Liu, <i>et al<\/i>.: \u201cA 10bit 320MS\/s low-cost SAR ADC for IEEE 802.11ac applications in 20nm CMOS,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2645 (DOI: 10.1109\/JSSC.2015.2466475).","DOI":"10.1109\/JSSC.2015.2466475"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] C.Y. Lin, <i>et al<\/i>.: \u201c27.5 an 80MHz-BW 640MS\/s time-interleaved passive noise-shaping SAR ADC in 22nm FDSOI process,\u201d IEEE Int. Solid-State Circuits Conf. (2021) 378 (DOI: 10.1109\/ISSCC42613.2021.9365754).","DOI":"10.1109\/ISSCC42613.2021.9365754"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] H. Zhang, <i>et al<\/i>.: \u201c27.6 a 25MHz-BW 75dB-SNDR inherent gain error tolerance noise-shaping SAR-assisted pipeline ADC with background offset calibration,\u201d IEEE Int. Solid-State Circuits Conf. (2021) 380 (DOI: 10.1109\/ISSCC42613.2021.9365833).","DOI":"10.1109\/ISSCC42613.2021.9365833"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A.H. Chang, <i>et al<\/i>.: \u201cA 12b 50MS\/s 2.1mW SAR ADC with redundancy and digital background calibration,\u201d European Solid-State Circuits Conf. (2013) 109 (DOI: 10.1109\/ESSCIRC.2013.6649084).","DOI":"10.1109\/ESSCIRC.2013.6649084"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] N.C. Chen, <i>et al<\/i>.: \u201cHigh-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC,\u201d Proc. Des., Auto. Test Europe (2017) 1757 (DOI: 10.23919\/DATE.2017.7927277).","DOI":"10.23919\/DATE.2017.7927277"},{"key":"6","unstructured":"[6] Y. Cao, <i>et al<\/i>.: \u201cA capacitor self-calibration technique for high resolution ADCs,\u201d IEEE Int. Conf. Solid-State Integr. Circuit Technol. (2016) 915 (DOI: 10.1109\/ICSICT.2016.7999078)."},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Ju, <i>et al<\/i>.: \u201cDigital calibration technique for subrange ADC based on SAR architecture,\u201d Int. Symp. Next-Gener. Electron. (2016) 1 (DOI: 10.1109\/ISNE.2016.7543358).","DOI":"10.1109\/ISNE.2016.7543358"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] X. Zhang, <i>et al<\/i>.: \u201cA 12-bit 200KS\/s SAR ADC with digital self-calibration,\u201d Proc. IEEE Adv. Inf. Technol. (2017) 2531 (DOI: 10.1109\/IAEAC.2017.8054480).","DOI":"10.1109\/IAEAC.2017.8054480"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T.C. Hung, <i>et al<\/i>.: \u201cA 12-bit time-interleaved 400-MS\/s pipelined ADC with split-ADC digital background calibration in 4,000 conversions\/channel,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>66<\/b> (2019) 1810 (DOI: 10.1109\/TCSII.2019.2895694).","DOI":"10.1109\/TCSII.2019.2895694"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] X. Gu, <i>et al<\/i>.: \u201cA calibration technique for SAR ADC based on code density test,\u201d Proc. IEEE Int. Conf. ASIC (2015) 1 (DOI: 10.1109\/ASICON.2015.7517110).","DOI":"10.1109\/ASICON.2015.7517110"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y. Zhu, <i>et al<\/i>.: \u201cHistogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120MS\/s SAR ADC,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 1203 (DOI: 10.1109\/TVLSI.2015.2442258).","DOI":"10.1109\/TVLSI.2015.2442258"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] M.A. Montazerolghaem, <i>et al<\/i>.: \u201cA predetermined LMS digital background calibration technique for pipelined ADCs,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>62<\/b> (2015) 841 (DOI: 10.1109\/TCSII.2015.2435071).","DOI":"10.1109\/TCSII.2015.2435071"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Z. Lan, <i>et al<\/i>.: \u201cA 12-bit 100MS\/s SAR ADC with digital error correction and high-speed LMS-based background calibration,\u201d Proc. IEEE Int. Symp. Circuits Syst. (2021) 1 (DOI: 10.1109\/ISCAS51556.2021.9401172).","DOI":"10.1109\/ISCAS51556.2021.9401172"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] W. Liu, <i>et al<\/i>.: \u201cA 12b 22.5\/45MS\/s 3.0mW 0.059mm<sup>2<\/sup> CMOS SAR ADC achieving over 90dB SFDR,\u201d IEEE Int. Solid-State Circuits Conf. (2010) 380 (DOI: 10.1109\/ISSCC.2010.5433830).","DOI":"10.1109\/ISSCC.2010.5433830"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] L. Wei, <i>et al<\/i>.: \u201cBackground LMS calibration algorithm realization for SAR-ADC,\u201d Int. Conf. Integr. Circuits Microsystems (2021) 142 (DOI: 10.1109\/ICICM54364.2021.9660322).","DOI":"10.1109\/ICICM54364.2021.9660322"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Y. Wang, <i>et al<\/i>.: \u201cDigital calibration of capacitor mismatch and gain error in pipelined SAR ADCs,\u201d Proc. Int. Conf. ASIC (2021) 1 (DOI: 10.1109\/ASICON52560.2021.9620474).","DOI":"10.1109\/ASICON52560.2021.9620474"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y.-S. Shu, <i>et al<\/i>.: \u201cAn oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS,\u201d IEEE Int. Solid-State Circuits Conf. (2016) 458 (DOI: 10.1109\/ISSCC.2016.7418105).","DOI":"10.1109\/ISSCC.2016.7418105"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J.H. Tsai, <i>et al<\/i>.: \u201cA 0.003mm<sup>2<\/sup> 10 b 240MS\/s 0.7mW SAR ADC in 28nm CMOS with digital error correction and correlated-reversed switching,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1382 (DOI: 10.1109\/JSSC.2015.2413850).","DOI":"10.1109\/JSSC.2015.2413850"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S.M. Zakharchenko, <i>et al<\/i>.: \u201cMethod of cyclic ADC calibration by the conversion characteristics analysis,\u201d Int. Conf. Adv. Inf. Commun. Technol. (2017) 120 (DOI: 10.1109\/AIACT.2017.8020079).","DOI":"10.1109\/AIACT.2017.8020079"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] H. Fan, <i>et al<\/i>.: \u201cCapacitive recombination calibration method to improve the performance of SAR ADC,\u201d Proc. IEEE Asia Pac. Conf. Circuits Syst. (2020) 43 (DOI: 10.1109\/APCCAS50809.2020.9301689).","DOI":"10.1109\/APCCAS50809.2020.9301689"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C.C. Lee, <i>et al<\/i>.: \u201cA 12b 70MS\/s SAR ADC with digital startup calibration in 14nm CMOS,\u201d IEEE Symp. VLSI Circuits Dig. Tech. Papers (2015) C62 (DOI: 10.1109\/VLSIC.2015.7231328).","DOI":"10.1109\/VLSIC.2015.7231328"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] C.C. Liu, <i>et al<\/i>.: \u201cA 10b 100MS\/s 1.13mW SAR ADC with binary-scaled error compensation,\u201d IEEE Int. Solid-State Circuits Conf. (2010) 386 (DOI: 10.1109\/ISSCC.2010.5433970).","DOI":"10.1109\/ISSCC.2010.5433970"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] X. Ding, <i>et al<\/i>.: \u201cRedundant double conversion based digital background calibration of SAR ADC with convergence acceleration and assistance,\u201d Proc. Int. Conf. Mixed Des. Integr. Circuits Syst. (2018) 192 (DOI: 10.23919\/MIXDES.2018.8436826).","DOI":"10.23919\/MIXDES.2018.8436826"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Rabuske, <i>et al<\/i>.: \u201cA 12-bit SAR ADC with background self-calibration based on a MOSCAP-DAC with dynamic body-biasing,\u201d Proc. IEEE Int. Symp. Circuits. Syst. (2016) 1482 (DOI: 10.1109\/ISCAS.2016.7527538).","DOI":"10.1109\/ISCAS.2016.7527538"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] H. Mafi, <i>et al<\/i>.: \u201cDigital calibration of elements mismatch in multirate predictive SAR ADCs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 4571 (DOI: 10.1109\/TCSI.2019.2931618).","DOI":"10.1109\/TCSI.2019.2931618"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] Q. Zhang, <i>et al<\/i>.: \u201cA 13-bit ENOB third-order noise-shaping SAR ADC employing hybrid error control structure and LMS-based foreground digital calibration,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 2181 (DOI: 10.1109\/JSSC.2021.3137540).","DOI":"10.1109\/JSSC.2021.3137540"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] A. Salib, <i>et al<\/i>.: \u201cA generic foreground calibration algorithm For ADCs with nonlinear impairments,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 1874 (DOI: 10.1109\/TCSI.2018.2870529).","DOI":"10.1109\/TCSI.2018.2870529"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Li, <i>et al<\/i>.: \u201cA second-order passive noise-shaping SAR ADC using the LMS-based mismatch calibration,\u201d Proc. Int. Conf. ASIC (2021) 1 (DOI: 10.1109\/ASICON52560.2021.9620468).","DOI":"10.1109\/ASICON52560.2021.9620468"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] A. Salib, <i>et al<\/i>.: \u201cBlind SAR ADC capacitor mismatch calibration,\u201d Midwest Symp. Circuits Syst. (2017) 587 (DOI: 10.1109\/MWSCAS.2017.8052991).","DOI":"10.1109\/MWSCAS.2017.8052991"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] L. Zhang, <i>et al<\/i>.: \u201cCorrelation-based background calibration of bit weight in SAR adcs using DAS algorithm,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 1063 (DOI: 10.1109\/TCSII.2020.3032182).","DOI":"10.1109\/TCSII.2020.3032182"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/16\/20_20.20230243\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,13]],"date-time":"2024-05-13T04:45:47Z","timestamp":1715575547000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/16\/20_20.20230243\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,25]]},"references-count":30,"journal-issue":{"issue":"16","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.20.20230243","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,8,25]]},"article-number":"20.20230243"}}