{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:07:49Z","timestamp":1776528469729,"version":"3.51.2"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"20","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2023,10,25]]},"DOI":"10.1587\/elex.20.20230385","type":"journal-article","created":{"date-parts":[[2023,9,14]],"date-time":"2023-09-14T22:54:08Z","timestamp":1694732048000},"page":"20230385-20230385","source":"Crossref","is-referenced-by-count":3,"title":["A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology"],"prefix":"10.1587","volume":"20","author":[{"given":"Zhichao","family":"Zhang","sequence":"first","affiliation":[{"name":"School of Electronic and Information Engineering, South China University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenjie","family":"Zheng","sequence":"additional","affiliation":[{"name":"School of Electronic and Information Engineering, South China University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinlin","family":"Xia","sequence":"additional","affiliation":[{"name":"School of Electronic and Information Engineering, South China University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yanjie","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electronic and Information Engineering, South China University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] N. Saito, <i>et al<\/i>.: \u201cA fully integrated 60-GHz CMOS transceiver chipset based on WiGig\/IEEE 802.11ad with built-in self calibration for mobile usage,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 3146 (DOI: 10.1109\/JSSC.2013.2279573).","DOI":"10.1109\/JSSC.2013.2279573"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Okada, <i>et al<\/i>.: \u201cFull four-channel 6.3-Gb\/s 60-GHz CMOS transceiver with low-power analog and digital baseband circuitry,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 46 (DOI: 10.1109\/JSS-C.2012.2218066).","DOI":"10.1109\/JSSC.2012.2218066"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] B. Jiang and H.C. Luong: \u201cA 23-mW 60-GHz differential sub-sampling PLL with an NMOS-only differential-inductively-tuned VCO,\u201d IEEE Asian Solid-State Circuits Conference (A-SSCC) (2019) 279 (DOI: 10.1109\/A-SSCC47793.2019.9056968).","DOI":"10.1109\/A-SSCC47793.2019.9056968"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] V. Szortyka, <i>et al<\/i>.: \u201cA 42mW 200fs-jitter 60GHz sub-sampling PLL in 40nm CMOS,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2025 (DOI: 10.1109\/JSSC.2015.2442998).","DOI":"10.1109\/JSSC.2015.2442998"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Y. Dong, <i>et al<\/i>.: \u201cA 2-GHz dual-path sub-sampling PLL with ring VCO phase noise suppression,\u201d IEEE Custom Integrated Circuits Conference (CICC) (2022) 1 (DOI: 10.1109\/CICC53496.2022.9772813).","DOI":"10.1109\/CICC53496.2022.9772813"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Sun, <i>et al<\/i>.: \u201cA type-II dual-path PLL with reference-spur suppression,\u201d IEEE Trans. Microw. Theory Techn. <b>70<\/b> (2022) 2280 (DOI: 10.1109\/TMTT.2022.3145369).","DOI":"10.1109\/TMTT.2022.3145369"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Z. Zhang, <i>et al<\/i>.: \u201cA 0.25-0.4-V, sub-0.11-mW\/GHz, 0.15-1.6-GHz PLL using an offset dual-path architecture with dynamic charge pumps,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 1871 (DOI: 10.1109\/JSSC.2020.3028376).","DOI":"10.1109\/JSSC.2020.3028376"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J. Lee and H. Wang: \u201cStudy of sub-harmonically injection-locked PLLs,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 1539 (DOI: 10.1109\/JSSC.2009.2016701).","DOI":"10.1109\/JSSC.2009.2016701"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] M. Seong, <i>et al<\/i>.: \u201cA 15-GHz, 17.8-mW, 213-fs injection-locked PLL with maximized injection strength using adjustment of phase domain response,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>66<\/b> (2019) 1932 (DOI: 10.1109\/TCSII.2019.2949555).","DOI":"10.1109\/TCSII.2019.2949555"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] M. Seong, <i>et al<\/i>.: \u201cAn optimum injection-timing tracking loop for 5-GHz, 1.13-mW\/GHz RO-based injection-locked PLL with 152-fs integrated jitter,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1819 (DOI: 10.1109\/TCSII.2018.2878565).","DOI":"10.1109\/TCSII.2018.2878565"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] C.Y. Lin, <i>et al<\/i>.: \u201cA 2.4-GHz 500-\u00b5W 370-fsrms integrated jitter sub-sampling sub-harmonically injection-locked PLL in 90-nm CMOS,\u201d IEEE Asian Solid-State Circuits Conference (A-SSCC) (2019) 91 (DOI: 10.1109\/A-SSCC47793.2019.9056964).","DOI":"10.1109\/A-SSCC47793.2019.9056964"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A.T. Narayanan, <i>et al<\/i>.: \u201cA fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB,\u201d European Solid-State Circuits Conference (ESSCIRC) (2015) 380 (DOI: 10.1109\/ESSCIRC.2015.7313907).","DOI":"10.1109\/ESSCIRC.2015.7313907"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y.C. Qian, <i>et al<\/i>.: \u201cA low-jitter sub-sampling PLL with a sub-sampling DLL,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 269 (DOI: 10.1109\/TCSII.2021.3105552).","DOI":"10.1109\/TCSII.2021.3105552"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] X. Gao, <i>et al<\/i>.: \u201cA low noise sub-sampling PLL in which divider noise is eliminated and PD\/CP noise is not multiplied by <i>N<\/i><sup>2<\/sup>,\u201d IEEE J. Solid-State Circuits <b>44<\/b> (2009) 3253 (DOI: 10.1109\/JSSC.2009.2032723).","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J. Sharma and H. Krishnaswamy: \u201cA 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1407 (DOI: 10.1109\/JSSC.2018.2889690).","DOI":"10.1109\/JSSC.2018.2889690"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] X. Gao, <i>et al<\/i>.: \u201cSpur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 1809 (DOI: 10.1109\/JSSC.2010.2053094).","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Z. Zhang, <i>et al<\/i>.: \u201cA 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and -256<i>.<\/i>4-dB FoM,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1665 (DOI: 10.1109\/JSSC.2020.2967562).","DOI":"10.1109\/JSSC.2020.2967562"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Z. Yang, <i>et al<\/i>.: \u201c16.8 A 25.4-to-29.5GHz 10.2mW isolated sub-sampling PLL achieving -252<i>.<\/i>9dB jitter-power FoM and -63dBc reference spur,\u201d IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers (2019) 270 (DOI: 10.1109\/ISSCC.2019.8662364).","DOI":"10.1109\/ISSCC.2019.8662364"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] D.G. Lee and P.P. Mercier: \u201cA sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of -256dB,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1542 (DOI: 10.1109\/JSSC.2019.2951377).","DOI":"10.1109\/JSSC.2019.2951377"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Z. Yang, <i>et al<\/i>.: \u201cA 3.3-GHz integer N-type-II sub-sampling PLL using a BFSK-suppressed push-pull SS-PD and a fast-locking FLL achieving -82<i>.<\/i>2-dBc REF spur and -255-dB FOM,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>30<\/b> (2022) 238 (DOI: 10.1109\/TVLSI.2021.3131219).","DOI":"10.1109\/TVLSI.2021.3131219"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y. Liu, <i>et al<\/i>.: \u201cA 24GHz PLL with low phase noise for 60GHz sliding-if transceiver in a 65-nm CMOS,\u201d Microelectronics Journal 113 (2021) 105106 (DOI: 10.1016\/j.mejo.2021.105106).","DOI":"10.1016\/j.mejo.2021.105106"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] E. Hegazi, <i>et al<\/i>.: \u201cA filtering technique to lower LC oscillator phase noise,\u201d IEEE J. Solid-State Circuits <b>36<\/b> (2001) 1921 (DOI: 10.1109\/4.972142).","DOI":"10.1109\/4.972142"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] F. Bozorgi, <i>et al<\/i>.: \u201cK-band class-B VCO in 22nm FD-SOI with inductive source degeneration of the tail current source,\u201d IEEE Microw. Wireless Compon. Lett. <b>32<\/b> (2022) 1351 (DOI: 10.1109\/LMWC.2022.3178916).","DOI":"10.1109\/LMWC.2022.3178916"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] M. Garampazzi, <i>et al<\/i>.: \u201cAnalysis and design of a 195.6dBc\/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1657 (DOI: 10.1109\/JSSC.2015.2413851).","DOI":"10.1109\/JSSC.2015.2413851"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] H. Wang and O. Momeni: \u201cA charge pump current mismatch compensation design for sub-sampling PLL,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 1852 (DOI: 10.1109\/TCSII.2021.3049365).","DOI":"10.1109\/TCSII.2021.3049365"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] K. Raczkowski, <i>et al<\/i>.: \u201cA 9.2-12.7GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1203 (DOI: 10.1109\/JSSC.2015.2403373).","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] Y. Zhang, <i>et al<\/i>.: \u201cA 23.6-38.3GHz low-noise PLL with digital ring oscillator and multi-ratio injection-locked dividers for millimeter-wave sensing,\u201d IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2020) 3 (DOI: 10.1109\/RFIC49505.2020.9218347).","DOI":"10.1109\/RFIC49505.2020.9218347"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] L. Grimaldi, <i>et al<\/i>.: \u201c16.7 A 30GHz digital sub-sampling fractional-N PLL with 198fsrms jitter in 65nm LP CMOS,\u201d IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers (2019) 268 (DOI: 10.1109\/ISSCC.2019.8662411).","DOI":"10.1109\/ISSCC.2019.8662411"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H. Wang and O. Momeni: \u201cLow-power and low-noise millimeter-wave SSPLL with subsampling lock detector for automatic dividerless frequency acquisition,\u201d IEEE Trans. Microw. Theory Techn. <b>69<\/b> (2021) 469 (DOI: 10.1109\/TMTT.2020.3039549).","DOI":"10.1109\/TMTT.2020.3039549"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Y. Hu, <i>et al<\/i>.: \u201c17.6 A 21.7-to-26.5GHz charge-sharing locking quadrature PLL with implicit digital frequency-tracking loop achieving 75fs jitter and -250dB FoM,\u201d IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers (2020) 276 (DOI: 10.1109\/ISSCC19947.2020.9063024).","DOI":"10.1109\/ISSCC19947.2020.9063024"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/20\/20_20.20230385\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T03:22:35Z","timestamp":1698463355000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/20\/20\/20_20.20230385\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,25]]},"references-count":30,"journal-issue":{"issue":"20","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.20.20230385","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,10,25]]},"article-number":"20.20230385"}}