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Roy, <i>et al<\/i>.: \u201cPLAKE: PUF-based secure lightweight authentication and key exchange protocol for IoT,\u201d IEEE Internet Things J. <b>10<\/b> (2022) 8547 (DOI: 10.1109\/JIOT.2022.3202265).","DOI":"10.1109\/JIOT.2022.3202265"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] C. Herder, <i>et al<\/i>.: \u201cPhysical unclonable functions and applications: a tutorial,\u201d Proc. IEEE <b>102<\/b> (2014) 1126 (DOI: 10.1109\/JPROC.2014.2320516).","DOI":"10.1109\/JPROC.2014.2320516"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Liu, <i>et al<\/i>.: \u201cA 0.04% BER strong PUF with cell-bias-based CRPs filtering and background offset calibration,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 3853 (DOI: 10.1109\/TCSI.2020.3008683).","DOI":"10.1109\/TCSI.2020.3008683"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] X. Xi, <i>et al<\/i>.: \u201cA provably secure strong PUF based on LWE: construction and implementation,\u201d IEEE Trans. Comput. <b>72<\/b> (2023) 346 (DOI: 10.1109\/TC.2022.3207119).","DOI":"10.1109\/TC.2022.3207119"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Shifman, <i>et al<\/i>.: \u201cPreselection methods to achieve very low BER in SRAM-based PUFs--a tutorial,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 2551 (DOI: 10.1109\/TCSII.2022.3170460).","DOI":"10.1109\/TCSII.2022.3170460"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Y. Wang, <i>et al<\/i>.: \u201cLattice PUF: a strong physical unclonable function provably secure against machine learning attacks,\u201d HOST (2020) 273 (DOI: 10.1109\/HOST45689.2020.9300270).","DOI":"10.1109\/HOST45689.2020.9300270"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Y. Guo, <i>et al<\/i>.: \u201cMulti-block APUF with 2-level voltage supply,\u201d ISVLSI (2018) 327 (DOI: 10.1109\/ISVLSI.2018.00067).","DOI":"10.1109\/ISVLSI.2018.00067"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] R. Della Sala, <i>et al<\/i>.: \u201cA lightweight FPGA compatible weak-PUF primitive based on XOR gates,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 2972 (DOI: 10.1109\/TCSII.2022.3156788).","DOI":"10.1109\/TCSII.2022.3156788"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Zhang, <i>et al<\/i>.: \u201cA 4T\/cell amplifier-chain-based XOR PUF with strong machine learning attack resilience,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2021) 366 (DOI: 10.1109\/TCSI.2021.3114084).","DOI":"10.1109\/TCSI.2021.3114084"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] L. Yu, <i>et al<\/i>.: \u201cInterconnect-based PUF with signature uniqueness enhancement,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>28<\/b> (2019) 339 (DOI: 10.1109\/TVLSI.2019.2943686).","DOI":"10.1109\/TVLSI.2019.2943686"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] R. Ali, <i>et al<\/i>.: \u201cA reconfigurable arbiter MPUF with high resistance against machine learning attack,\u201d IEEE Trans. Magn. <b>57<\/b> (2021) 1 (DOI: 10.1109\/TMAG.2021.3102838).","DOI":"10.1109\/TMAG.2021.3102838"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] D.P. Sahoo, <i>et al<\/i>.: \u201cA multiplexer-based arbiter PUF composition with enhanced reliability and security,\u201d IEEE Trans. Comput. <b>67<\/b> (2017) 403 (DOI: 10.1109\/TC.2017.2749226).","DOI":"10.1109\/TC.2017.2749226"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] W. Ge, <i>et al<\/i>.: \u201cFPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance,\u201d IEICE Electron. Express <b>17<\/b> (2019) 20190670 (DOI: 10.1587\/elex.16.20190670).","DOI":"10.1587\/elex.16.20190670"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] S. Shariffuddin, <i>et al<\/i>.: \u201cReview on arbiter physical unclonable function and its implementation in FPGA for IoT security applications,\u201d ICDCS (2022) 369 (DOI: 10.1109\/ICDCS54290.2022.9780766).","DOI":"10.1109\/ICDCS54290.2022.9780766"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Z. Zhou, <i>et al<\/i>.: \u201cBagua protocol: a whole-process configurable protocol for IoT sensing devices security based on strong PUF,\u201d IEEE Internet Things J. (2023) 1 (DOI: 10.1109\/JIOT.2023.3285930).","DOI":"10.1109\/JIOT.2023.3285930"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] N. Shah, <i>et al<\/i>.: \u201cIntroducing recurrence in strong PUFs for enhanced machine learning attack resistance,\u201d IEEE J. Emerg. Sel. Topics Circuits Syst. <b>11<\/b> (2021) 319 (DOI: 10.1109\/JETCAS.2021.3075767).","DOI":"10.1109\/JETCAS.2021.3075767"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Xu, <i>et al<\/i>.: \u201cModeling attack resistant strong PUF exploiting stagewise obfuscated interconnections with improved reliability,\u201d IEEE Internet Things J. <b>10<\/b> (2023) 16300 (DOI: 10.1109\/JIOT.2023.3267657).","DOI":"10.1109\/JIOT.2023.3267657"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] L. Zufeng, <i>et al<\/i>.: \u201cLDCPUF: a novel FPGA-based physical unclonable function with ultra-low hardware cost,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220246 (DOI: 10.1587\/elex.19.20220246).","DOI":"10.1587\/elex.19.20220246"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Wang, <i>et al<\/i>.: \u201cNoPUF: a novel PUF design framework toward modeling attack resistant PUFs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 2508 (DOI: 10.1109\/TCSI.2021.3067319).","DOI":"10.1109\/TCSI.2021.3067319"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] B. Thapaliya, <i>et al<\/i>.: \u201cMachine learning-based vulnerability study of interpose PUFs as security primitives for IoT networks,\u201d NAS (2021) 1 (DOI: 10.1109\/NAS51552.2021.9605405).","DOI":"10.1109\/NAS51552.2021.9605405"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] C.-Y. Lee, <i>et al<\/i>.: \u201cNIST-Lite: randomness testing of RNGs on an energy-constrained platform,\u201d ICCD (2021) 41 (DOI: 10.1109\/ICCD53106.2021.00019).","DOI":"10.1109\/ICCD53106.2021.00019"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] G. Li, <i>et al<\/i>.: \u201cA 215-F<sup>2<\/sup> bistable physically unclonable function with an ACF of <i>&lt;<\/i>0<i>.<\/i>005 and a native bit instability of 2.05% in 65-nm CMOS process,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>28<\/b> (2020) 2290 (DOI: 10.1109\/TVLSI.2020.3014892).","DOI":"10.1109\/TVLSI.2020.3014892"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. Liu, <i>et al<\/i>.: \u201cA weak PUF-assisted strong PUF with inherent immunity to modeling attacks and ultra-low BER,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 4898 (DOI: 10.1109\/TCSI.2022.3206214).","DOI":"10.1109\/TCSI.2022.3206214"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Singh, <i>et al<\/i>.: \u201cPA-PUF: a novel priority arbiter PUF,\u201d VLSI-SoC (2022) (DOI: 10.1109\/VLSI-SoC54400.2022.9939642).","DOI":"10.1109\/VLSI-SoC54400.2022.9939642"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] E. Elmitwalli, <i>et al<\/i>.: \u201cMachine learning attack resistant area-efficient reconfigurable ising-PUF,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>30<\/b> (2022) 526 (DOI: 10.1109\/TVLSI.2022.3144236).","DOI":"10.1109\/TVLSI.2022.3144236"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H. Wang, <i>et al<\/i>.: \u201cModeling challenge covariances and design dependency for efficient attacks on strong PUFs,\u201d ITC (2022) (DOI: 10.1109\/ITC50671.2022.00007).","DOI":"10.1109\/ITC50671.2022.00007"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] J. Yao, <i>et al<\/i>.: \u201cDesign and evaluate recomposited OR-AND-XOR-PUF,\u201d IEEE Trans. Emerg. Topics Comput. (2022) 1 (DOI: 10.1109\/TETC.2022.3170320).","DOI":"10.1109\/TETC.2022.3170320"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] X. Xi, <i>et al<\/i>.: \u201cStrong subthreshold current array PUF with 2<sup>65<\/sup> challenge-response pairs resilient to machine learning attacks in 130nm CMOS,\u201d Symposium on VLSI Circuits (2017) C268 (DOI: 10.23919\/VLSIC.2017.8008503).","DOI":"10.23919\/VLSIC.2017.8008503"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/2\/21_20.20230458\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,27]],"date-time":"2024-01-27T03:16:19Z","timestamp":1706325379000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/2\/21_20.20230458\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1,25]]},"references-count":31,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.20.20230458","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2024,1,25]]},"article-number":"20.20230458"}}