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Boutros and V. Betz: \u201cFPGA architecture: Principles and progression,\u201d IEEE Circuits Syst. Mag. <b>21<\/b> (2021) 4 (DOI: 10.1109\/mcas.2021.3071607).","DOI":"10.1109\/MCAS.2021.3071607"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Brown and J. Rose: \u201cFPGA and CPLD architectures: A tutorial,\u201d IEEE Des. Test Comput. <b>13<\/b> (1996) 42 (DOI: 10.1109\/54.500200).","DOI":"10.1109\/54.500200"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] I. Kuon, <i>et al<\/i>.: \u201cFPGA architecture: Survey and challenges,\u201d Foundations and Trends in Electronic Design Automation <b>2<\/b> (2008) 135 (DOI: 10.1561\/1000000005).","DOI":"10.1561\/1000000005"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] U. Farooq, <i>et al<\/i>.: \u201cFPGA architectures: An overview,\u201d <i>Tree-Based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization<\/i> (Springer, New York, NY, 2012) 7 (DOI: 10.1007\/978-1-4614-3594-5_2).","DOI":"10.1007\/978-1-4614-3594-5"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Gandhare and B. Karthikeyan: \u201cSurvey on FPGA architecture and recent applications,\u201d 2019 IEEE International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN) (2019) 1 (DOI: 10.1109\/vitecon.2019.8899550).","DOI":"10.1109\/ViTECoN.2019.8899550"},{"key":"6","unstructured":"[6] VTR: https:\/\/github.com\/verilog-to-routing\/vtr-verilog-to-routing"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] D. Lewis, <i>et al<\/i>.: \u201cArchitectural enhancements in Stratix V<sup>TM<\/sup>,\u201d Proc. ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (2013) (DOI: 10.1145\/2435264.2435292).","DOI":"10.1145\/2435264.2435292"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] S.D. Brown, <i>et al<\/i>.: \u201cA stochastic model to predict the routability of field-programmable gate arrays,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. <b>12<\/b> (1993) 1827 (DOI: 10.1109\/43.251146).","DOI":"10.1109\/43.251146"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J. Das and S.J.E. Wilton: \u201cAn analytical model relating FPGA architecture parameters to routability,\u201d Proc. 19th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (2011) 181 (DOI: 10.1145\/1950413.1950449).","DOI":"10.1145\/1950413.1950449"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] O. Petelin and V. Betz: \u201cWotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks,\u201d 2015 25th IEEE International Conference on Field Programmable Logic and Applications (FPL) (2015) 1 (DOI: 10.1109\/fpl.2015.7294008).","DOI":"10.1109\/FPL.2015.7294008"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J.W. Greene: \u201cFPGA mux usage and routability estimates without explicit routing,\u201d Proc. 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (2023) 141 (DOI: 10.1145\/3543622.3573045).","DOI":"10.1145\/3543622.3573045"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Wang, <i>et al<\/i>.: \u201cFPGA interconnect architecture exploration based on a statistical model,\u201d 2011 21st IEEE International Conference on Field Programmable Logic and Applications (2011) 447 (DOI: 10.1109\/fpl.2011.88).","DOI":"10.1109\/FPL.2011.88"},{"key":"13","unstructured":"[13] V. Betz, <i>et al<\/i>.: <i>Architecture and CAD for Deep-Submicron FPGAs<\/i>, (Springer Science &amp; Business Media, 2012) (DOI: 10.1007\/978-1-4615-5145-4)."},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] J. Rose and S. Brown: \u201cFlexibility of interconnection structures for field-programmable gate arrays,\u201d IEEE J. Solid-State Circuits <b>26<\/b> (1991) 277 (DOI: 10.1109\/4.75006).","DOI":"10.1109\/4.75006"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Y.W. Chang, <i>et al<\/i>.: \u201cUniversal switch modules for FPGA design,\u201d ACM Trans. Des. Autom. Electron. Syst. (TODAES) <b>1<\/b> (1996) 80 (DOI: 10.1145\/225871.225886).","DOI":"10.1145\/225871.225886"},{"key":"16","unstructured":"[16] S.J.E. Wilton, <i>Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory<\/i> (Toronto, Ontario, Canada: University of Toronto, 1997)."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] C. Hu, <i>et al<\/i>.: \u201cA tile-based interconnect model for FPGA architecture exploration,\u201d Proc. 2020 on Great Lakes Symposium on VLSI (2020) 113 (DOI: 10.1145\/3386263.3406927).","DOI":"10.1145\/3386263.3406927"},{"key":"18","unstructured":"[18] T.J. Bauer and S.P. Young: U.S. Patent no.7,202,698 (2007)."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] Y. Shen, <i>et al<\/i>.: \u201cTwo-level MUX design and exploration in FPGA routing architecture,\u201d 2021 31st IEEE International Conference on Field-Programmable Logic and Applications (FPL) (2021) (DOI: 10.1109\/fpl53798.2021.00045).","DOI":"10.1109\/FPL53798.2021.00045"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Y. Li, <i>et al<\/i>.: \u201cAutoTEA: automated transistor-level efficient and accurate optimization for GRM FPGA design,\u201d 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2021) (DOI: 10.1109\/fccm51124.2021.00043).","DOI":"10.1109\/FCCM51124.2021.00043"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Z. Li, <i>et al<\/i>.: \u201cAn automatic transistor-level tool for GRM FPGA interconnect circuits optimization,\u201d Proc. 2019 on Great Lakes Symposium on VLSI (2019) 93 (DOI: 10.1145\/3299874.3318003).","DOI":"10.1145\/3299874.3318003"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] M.O. Ball, <i>et al<\/i>.: \u201cNetwork reliability,\u201d <i>Handbooks in Operations Research and Management Science<\/i> <b>7<\/b> (Elsevier, 1995) 673 (DOI: 10.1016\/s0927-0507(05)80128-8).","DOI":"10.1016\/S0927-0507(05)80128-8"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M.O. Ball: \u201cComplexity of network reliability computations,\u201d Networks <b>10<\/b> (1980) 153 (DOI: 10.1002\/net.3230100206).","DOI":"10.1002\/net.3230100206"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] A. Satyanarayana and M.K. Chang: \u201cNetwork reliability and the factoring theorem,\u201d Networks <b>13<\/b> (1983) 107 (DOI: 10.1002\/net.3230130107).","DOI":"10.1002\/net.3230130107"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] I.B. Gertsbakh and Y. Shpungin: <i>Models of Network Reliability: Analysis, Combinatorics, and Monte Carlo<\/i> (CRC Press, 2016) (DOI: 10.1201\/b12536).","DOI":"10.1201\/b12536"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] M.B. Petersen, <i>et al<\/i>.: \u201cNetCracker: A peek into the routing architecture of Xilinx 7-Series FPGAs,\u201d The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (2021) 11 (DOI: 10.1145\/3431920.3439285).","DOI":"10.1145\/3431920.3439285"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] J. Chromczak, <i>et al<\/i>.: \u201cArchitectural enhancements in Intel\u00ae Agilex<sup>TM<\/sup> FPGAs,\u201d Proc. 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (2020) 140 (DOI: 10.1145\/3373087.3375308).","DOI":"10.1145\/3373087.3375308"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] K.E. Murray, <i>et al<\/i>.: \u201cVTR 8: High-performance cad and customizable FPGA architecture modelling,\u201d ACM Trans. Reconfigurable Technol. Syst. (TRETS) <b>13<\/b> (2020) 1 (DOI: 10.1145\/3388617).","DOI":"10.1145\/3388617"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] A.M. Bigatti, <i>et al<\/i>.: \u201cA C++ class for multi-state algebraic reliability computations,\u201d Reliability Engineering &amp; System Safety <b>213<\/b> (2021) 107751 (DOI: 10.1016\/j.ress.2021.107751).","DOI":"10.1016\/j.ress.2021.107751"},{"key":"30","unstructured":"[30] R.S. Witte and J.S. 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