{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,7]],"date-time":"2026-09-07T23:00:24Z","timestamp":1788822024382,"version":"build-2803163510"},"reference-count":32,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,2,10]]},"DOI":"10.1587\/elex.20.20230557","type":"journal-article","created":{"date-parts":[[2023,12,19]],"date-time":"2023-12-19T22:12:37Z","timestamp":1703023957000},"page":"20230557-20230557","source":"Crossref","is-referenced-by-count":3,"title":["A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain"],"prefix":"10.1587","volume":"21","author":[{"given":"Ya","family":"Hai","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fei","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongshan","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] H.J. Kim, <i>et al.<\/i>: \u201c1GB\/s 2Tb nand flash multi-chip package with frequency-boosting interface chip,\u201d ISSCC Dig. Tech. Papers (2015) 1 (DOI: 10.1109\/ISSCC.2015.7062964).","DOI":"10.1109\/ISSCC.2015.7062964"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H.J. Kim, <i>et al.<\/i>: \u201cA 1.2V 1.33Gb\/s\/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high-performance storage applications,\u201d Symposium on VLSI Circuits (2017) C194 (DOI: 10.23919\/VLSIC.2017.8008479).","DOI":"10.23919\/VLSIC.2017.8008479"},{"key":"3","unstructured":"[3] D. Kang, <i>et al.<\/i>: \u201cA 512Gb 3-bit\/cell 3D 6th-generation V-NAND Flash memory with 82MB\/s write throughput and 1.2Gb\/s interface,\u201d ISSCC Dig. Tech. Papers (2019) 216 (DOI: 10.1109\/ISSCC.2019.8662493)."},{"key":"4","unstructured":"[4] D.-H. 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Ke, <i>et al<\/i>.: \u201cA high-resolution all-digital duty-cycle corrector with a new pulse-width detector,\u201d IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) (2010) 1 (DOI: 10.1109\/EDSSC.2010.5713749)."}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/3\/21_20.20230557\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,13]],"date-time":"2024-05-13T04:50:05Z","timestamp":1715575805000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/3\/21_20.20230557\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,2,10]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.20.20230557","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,2,10]]},"article-number":"20.20230557"}}