{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T00:03:17Z","timestamp":1774742597428,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,8,10]]},"DOI":"10.1587\/elex.21.20240099","type":"journal-article","created":{"date-parts":[[2024,4,15]],"date-time":"2024-04-15T22:16:20Z","timestamp":1713219380000},"page":"20240099-20240099","source":"Crossref","is-referenced-by-count":1,"title":["A 200-Gb\/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process"],"prefix":"10.1587","volume":"21","author":[{"given":"Sijie","family":"Fan","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of integrated circuits, University of Chinese Academy of Sciences"}]},{"given":"Zedong","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of integrated circuits, University of Chinese Academy of Sciences"}]},{"given":"Hua","family":"Xu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of integrated circuits, University of Chinese Academy of Sciences"}]},{"given":"Hengyu","family":"Xu","sequence":"additional","affiliation":[{"name":"Beijing Institute of Smart Energy"}]},{"given":"Wenxiang","family":"Zhen","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of integrated circuits, University of Chinese Academy of Sciences"}]},{"given":"Xuqiang","family":"Zheng","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of integrated circuits, University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] M. Nagatani, <i>et al.<\/i>: \u201c110-GHz-bandwidth InP-HBT AMUX\/ADEMUX circuits for beyond-1-Tb\/s\/ch digital coherent optical transceivers,\u201d 2022 IEEE Custom Integrated Circuits Conference (CICC) (2022) 1 (DOI: 10.1109\/CICC53496.2022.9772800).","DOI":"10.1109\/CICC53496.2022.9772800"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] R.L. Nguyen, <i>et al.<\/i>: \u201cA highly reconfigurable 40-97GS\/s DAC and ADC with 40GHz AFE bandwidth and sub-35fJ\/conv-step for 400Gb\/s coherent optical applications in 7nm FinFET,\u201d 2021 IEEE International Solid-State Circuits Conference (ISSCC) (2021) 136 (DOI: 10.1109\/ISSCC42613.2021.9365746).","DOI":"10.1109\/ISSCC42613.2021.9365746"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] T. 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(VLSI) Syst. <b>12<\/b> (2004) 1081 (DOI: 10.1109\/TVLSI.2004.833663).","DOI":"10.1109\/TVLSI.2004.833663"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/15\/21_21.20240099\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T03:27:16Z","timestamp":1723260436000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/15\/21_21.20240099\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,10]]},"references-count":33,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240099","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,8,10]]},"article-number":"21.20240099"}}