{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,27]],"date-time":"2025-12-27T03:43:37Z","timestamp":1766807017214},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,4,10]]},"DOI":"10.1587\/elex.21.20240104","type":"journal-article","created":{"date-parts":[[2024,3,5]],"date-time":"2024-03-05T22:12:03Z","timestamp":1709676723000},"page":"20240104-20240104","source":"Crossref","is-referenced-by-count":3,"title":["A high-output-swing 64-Gb\/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS"],"prefix":"10.1587","volume":"21","author":[{"given":"Hua","family":"Xu","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Xuqiang","family":"Zheng","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Zedong","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Chen","family":"Cai","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Wenxiang","family":"Zhen","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Guojun","family":"Yuan","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences"},{"name":"Wuxi Institute of Interconnect Technology"}]},{"given":"Qinfen","family":"Hao","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology Chinese Academy of Sciences"},{"name":"Wuxi Institute of Interconnect Technology"}]},{"given":"Xuan","family":"Guo","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Zhi","family":"Jin","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] K. Zhu, <i>et al.<\/i>: \u201cA 25Gb\/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20220527 (DOI: 10.1587\/elex.19.20220527).","DOI":"10.1587\/elex.19.20220527"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Sun, <i>et al.<\/i>: \u201c6.25-10Gb\/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18\u00b5m CMOS,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220429 (DOI: 10.1587\/elex.19.20220429).","DOI":"10.1587\/elex.19.20220429"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Kang and J. Song: \u201cA 0.88-pJ\/bit 28Gb\/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210253 (DOI: 10.1587\/elex.18.20210253).","DOI":"10.1587\/elex.18.20210253"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Zhang and X. Yang: \u201cA 36Gb\/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13\u00b5m BiCMOS technology,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200009 (DOI: 10.1587\/elex.17.20200009).","DOI":"10.1587\/elex.17.20200009"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Z. Guo, <i>et al.<\/i>: \u201cA 112.5Gb\/s ADC-DSP-based PAM-4 long-reach transceiver with <i>&gt;<\/i>50dB channel loss in 5nm FinFET,\u201d ISSCC Dig. Tech. Papers (2022) 116 (DOI: 10.1109\/ISSCC42614.2022.9731650).","DOI":"10.1109\/ISSCC42614.2022.9731650"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] N. Kocaman, <i>et al.<\/i>: \u201cAn 182mW 1-60Gb\/s configurable PAM-4\/NRZ transceiver for large scale ASIC integration in 7nm FinFET technology,\u201d ISSCC Dig. Tech. Papers (2022) 120 (DOI: 10.1109\/ISSCC42614.2022.9731688).","DOI":"10.1109\/ISSCC42614.2022.9731688"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Choi, <i>et al.<\/i>: \u201cAn output-bandwidth-optimized 200Gb\/s PAM-4 100Gb\/s NRZ transmitter with 5-tap FFE in 28nm CMOS,\u201d ISSCC Dig. Tech. Papers (2021) 128 (DOI: 10.1109\/ISSCC42613.2021.9366012).","DOI":"10.1109\/ISSCC42613.2021.9366012"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] P. Mishra, <i>et al.<\/i>: \u201cA 112Gb\/s ADC-DSP-based PAM-4 transceiver for long-reach applications with <i>&gt;<\/i>40dB channel loss in 7nm FinFET,\u201d ISSCC Dig. Tech. Papers (2021) 138 (DOI: 10.1109\/ISSCC42613.2021.9365929).","DOI":"10.1109\/ISSCC42613.2021.9365929"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] W. Han, <i>et al.<\/i>: \u201cA 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210302 (DOI: 10.1587\/elex.18.20210302).","DOI":"10.1587\/elex.18.20210302"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] W. Fan, <i>et al.<\/i>: \u201c4-channel, 224Gb\/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230386 (DOI: 10.1587\/elex.20.20230386).","DOI":"10.1587\/elex.20.20230386"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Xie, <i>et al.<\/i>: \u201cLow jitter design for quarter-rate CDR of 100Gb\/s PAM4 optical receiver,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220281 (DOI: 10.1587\/elex.19.20220281).","DOI":"10.1587\/elex.19.20220281"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] T. Yoshimatsu, <i>et al.<\/i>: \u201cDispersion tolerance of 100-Gbit\/s PAM4 optical link utilizing high-speed avalanche photodiode receiver,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180624 (DOI: 10.1587\/elex.15.20180624).","DOI":"10.1587\/elex.15.20180624"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] T. Ali, <i>et al.<\/i>: \u201cA 460mW 112Gb\/s DSP-based transceiver with 38dB loss compensation for next-generation data centers in 7nm FinFET technology,\u201d ISSCC Dig. Tech. Papers (2020) 118 (DOI: 10.1109\/ISSCC19947.2020.9062925).","DOI":"10.1109\/ISSCC19947.2020.9062925"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] E. Depaoli, <i>et al.<\/i>: \u201cA 64Gb\/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 6 (DOI: 10.1109\/JSSC.2018.2873602).","DOI":"10.1109\/JSSC.2018.2873602"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Y. Chang, <i>et al.<\/i>: \u201cAn 80-Gb\/s 44-mW wireline PAM4 transmitter,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 2214 (DOI: 10.1109\/JSSC.2018.2831226).","DOI":"10.1109\/JSSC.2018.2831226"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] E. Depaoli, <i>et al.<\/i>: \u201cA 4.9pJ\/b 16-to-64Gb\/s PAM-4 VSR transceiver in 28nm FDSOI CMOS,\u201d ISSCC Dig. Tech. Papers (2018) 112 (DOI: 10.1109\/ISSCC.2018.8310209).","DOI":"10.1109\/ISSCC.2018.8310209"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] S. Jeon, <i>et al.<\/i>: \u201cA framed-pulsewidth modulation transceiver for high-speed broadband communication links,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 2825 (DOI: 10.1109\/TCSI.2020.2982050).","DOI":"10.1109\/TCSI.2020.2982050"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J. Kim, <i>et al.<\/i>: \u201cA 224-Gb\/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 6 (DOI: 10.1109\/JSSC.2021.3108969).","DOI":"10.1109\/JSSC.2021.3108969"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] T. Norimatsu, <i>et al.<\/i>: \u201cA 100-Gbps 4-lane transceiver for 47-dB loss copper cable in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 3433 (DOI: 10.1109\/TCSI.2020.2993569).","DOI":"10.1109\/TCSI.2020.2993569"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Y. Chen, <i>et al.<\/i>: \u201cA 36-Gb\/s 1.3-mW\/Gb\/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>65<\/b> (2018) 3014 (DOI: 10.1109\/TCSI.2018.2829725).","DOI":"10.1109\/TCSI.2018.2829725"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] P.-J. Peng, <i>et al.<\/i>: \u201cA 112-Gb\/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 2123 (DOI: 10.1109\/JSSC.2020.3038818).","DOI":"10.1109\/JSSC.2020.3038818"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] G. Steffan, <i>et al.<\/i>: \u201cA 64Gb\/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ\/b energy efficiency in 28nm CMOS FDSOI,\u201d ISSCC Dig. Tech. Papers (2017) 116 (DOI: 10.1109\/ISSCC.2017.7870288).","DOI":"10.1109\/ISSCC.2017.7870288"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M. Bassi, <i>et al.<\/i>: \u201cA 45Gb\/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI,\u201d ISSCC Dig. Tech. Papers (2016) 66 (DOI: 10.1109\/ISSCC.2016.7417909).","DOI":"10.1109\/ISSCC.2016.7417909"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] F. Celik, <i>et al.<\/i>: \u201cA 32-Gb\/s PAM-4 SST transmitter with four-tap FFE using high-impedance driver in 28-nm FDSOI,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 1132 (DOI: 10.1109\/TVLSI.2021.3068242).","DOI":"10.1109\/TVLSI.2021.3068242"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] R. Shivnaraine, <i>et al.<\/i>: \u201cA 26.5625-to-106.25Gb\/s XSR SerDes with 1.55pJ\/b efficiency in 7nm CMOS,\u201d ISSCC Dig. Tech. Papers (2021) 181 (DOI: 10.1109\/ISSCC42613.2021.9365975).","DOI":"10.1109\/ISSCC42613.2021.9365975"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] C. Fan, <i>et al.<\/i>: \u201cA 40-Gb\/s PAM-4 transmitter using a 0.16-pJ\/bit SST-CML-hybrid (SCH) output driver and a hybrid-path 3-tap FFE scheme in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 4850 (DOI: 10.1109\/TCSI.2019.2936226).","DOI":"10.1109\/TCSI.2019.2936226"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] C. Cai, <i>et al.<\/i>: \u201cA 1.4-Vppd 64-Gb\/s PAM-4 transmitter with 4-tap hybrid FFE employing fractionally-spaced pre-emphasis and baud-spaced de-emphasis in 28-nm CMOS,\u201d ESSCIRC (2021) 527 (DOI: 10.1109\/ESSCIRC53450.2021.9567818).","DOI":"10.1109\/ESSCIRC53450.2021.9567818"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] Y. Frans, <i>et al.<\/i>: \u201cA 56-Gb\/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 1101 (DOI: 10.1109\/JSSC.2016.2632300).","DOI":"10.1109\/JSSC.2016.2632300"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] T.O. Dickson, <i>et al.<\/i>: \u201cA 1.8pJ\/b 56Gb\/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS,\u201d ISSCC Dig. Tech. Papers (2017) (DOI: 10.1109\/ISSCC.2017.7870289).","DOI":"10.1109\/ISSCC.2017.7870289"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] B.-J. Yoo, <i>et al.<\/i>: \u201cA 56Gb\/s 7.7mW\/Gb\/s PAM-4 wireline transceiver in 10nm FinFET using MM-CDR-based ADC timing skew control and low-power DSP with approximate multiplier,\u201d ISSCC Dig. Tech. Papers (2020) 122 (DOI: 10.1109\/ISSCC19947.2020.9062964).","DOI":"10.1109\/ISSCC19947.2020.9062964"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/7\/21_21.20240104\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,13]],"date-time":"2024-04-13T03:32:11Z","timestamp":1712979131000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/7\/21_21.20240104\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,10]]},"references-count":30,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240104","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,4,10]]},"article-number":"21.20240104"}}