{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T15:42:02Z","timestamp":1773330122660,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,5,10]]},"DOI":"10.1587\/elex.21.20240194","type":"journal-article","created":{"date-parts":[[2024,4,9]],"date-time":"2024-04-09T22:24:33Z","timestamp":1712701473000},"page":"20240194-20240194","source":"Crossref","is-referenced-by-count":7,"title":["Power, performance, and area evaluation across 180nm-28nm technology nodes based on benchmark circuits"],"prefix":"10.1587","volume":"21","author":[{"given":"Minghui","family":"Yin","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiqiang","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weihua","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongwei","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huanhuan","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunxia","family":"You","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] International Roadmap for Devices and Systems: IEEE IRDS<sup>TM<\/sup> (2022 Edition) (2022) https:\/\/irds.ieee.org\/editions\/2022"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H.N. 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