{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,13]],"date-time":"2024-07-13T04:10:37Z","timestamp":1720843837366},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,7,10]]},"DOI":"10.1587\/elex.21.20240247","type":"journal-article","created":{"date-parts":[[2024,6,4]],"date-time":"2024-06-04T22:11:06Z","timestamp":1717539066000},"page":"20240247-20240247","source":"Crossref","is-referenced-by-count":0,"title":["Frequency dependence of soft error rates induced by alpha-particle and heavy ion"],"prefix":"10.1587","volume":"21","author":[{"given":"Haruto","family":"Sugisaki","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryuichi","family":"Nakajima","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shotaro","family":"Sugitani","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Furuta","sequence":"additional","affiliation":[{"name":"Graduate School of Computer Science and Systems Engineering, Okayama Prefectural University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazutoshi","family":"Kobayashi","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] R. Baumann: \u201cThe impact of technology scaling on soft error rate performance and limits to the efficacy of error correction,\u201d Digest International Electron Devices Meeting (2002) 329 (DOI: 10.1109\/iedm.2002.1175845)."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] G.E. Moore: \u201cCramming more components onto integrated circuits, reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff,\u201d IEEE Solid-State Circuits Soc. Newslett. <b>11<\/b> (2006) 33 (DOI: 10.1109\/n-ssc.2006.4785860).","DOI":"10.1109\/N-SSC.2006.4785860"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] T. Heijmen, <i>et al.<\/i>: \u201cA comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries,\u201d IEEE Trans. Device Mater. Rel. <b>7<\/b> (2007) 84 (DOI: 10.1109\/tdmr.2007.897517).","DOI":"10.1109\/TDMR.2007.897517"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] R.C. Baumann: \u201cRadiation-induced soft errors in advanced semiconductor technologies,\u201d IEEE Trans. Device Mater. Rel. <b>5<\/b> (2005) 305 (DOI: 10.1109\/tdmr.2005.853449).","DOI":"10.1109\/TDMR.2005.853449"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Baumann: \u201cSoft errors in advanced computer systems,\u201d IEEE Des. Test Comput. <b>22<\/b> (2005) 258 (DOI: 10.1109\/mdt.2005.69).","DOI":"10.1109\/MDT.2005.69"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] M. Nicolaidis: \u201cDesign for soft error mitigation,\u201d IEEE Trans. Device Mater. Rel. <b>5<\/b> (2005) 405 (DOI: 10.1109\/tdmr.2005.855790).","DOI":"10.1109\/TDMR.2005.855790"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] S. Buchner, <i>et al.<\/i>: \u201cComparison of error rates in combinational and sequential logic,\u201d IEEE Trans. Nucl. Sci. <b>44<\/b> (1997) 2209 (DOI: 10.1109\/23.659037).","DOI":"10.1109\/23.659037"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J.R. Ahlbin, <i>et al.<\/i>: \u201cC-CREST technique for combinational logic SET testing,\u201d IEEE Trans. Nucl. Sci. <b>55<\/b> (2008) 3347 (DOI: 10.1109\/tns.2008.2005900).","DOI":"10.1109\/TNS.2008.2005900"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T. Calin, <i>et al<\/i>.: \u201cUpset hardened memory design for submicron CMOS technology,\u201d IEEE Trans. Nucl. Sci. <b>43<\/b> (1996) 2874 (DOI: 10.1109\/23.556880).","DOI":"10.1109\/23.556880"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] F. Mori, <i>et al<\/i>.: \u201cIntrinsic vulnerability to soft errors and a mitigation technique by layout optimization on DICE flip flops in a 65-nm bulk process,\u201d IEEE Trans. Nucl. Sci. <b>68<\/b> (2021) 1727 (DOI: 10.1109\/tns.2021.3075176).","DOI":"10.1109\/TNS.2021.3075176"},{"key":"11","unstructured":"[11] D.G. Mavis and P.H. Eaton: \u201cSoft error rate mitigation techniques for modern microcircuits,\u201d Proc. 2002 IEEE International Reliability Physics Symposium (2002) 216 (DOI: 10.1109\/relphy.2002.996639)."},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] K. Kobayashi, <i>et al.<\/i>: \u201cA low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65nm thin-BOX FD-SOI,\u201d IEEE Trans. Nucl. Sci. <b>61<\/b> (2014) 1881 (DOI: 10.1109\/tns.2014.2318326).","DOI":"10.1109\/TNS.2014.2318326"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S.M. Jahinuzzaman, <i>et al<\/i>.: \u201cA soft error tolerant 10T SRAM bit-cell with differential read capability,\u201d IEEE Trans. Nucl. Sci. <b>56<\/b> (2009) 3768 (DOI: 10.1109\/tns.2009.2032090).","DOI":"10.1109\/TNS.2009.2032090"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y.-Q. Li, <i>et al.<\/i>: \u201cA quatro-based 65-nm flip-flop circuit for soft-error resilience,\u201d IEEE Trans. Nucl. Sci. <b>64<\/b> (2017) 1554 (DOI: 10.1109\/tns.2017.2704062).","DOI":"10.1109\/TNS.2017.2704062"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M.J. Gadlage, <i>et al.<\/i>: \u201cIncreased single-event transient pulsewidths in a 90-nm bulk CMOS technology operating at elevated temperatures,\u201d IEEE Trans. Device Mater. Rel. <b>10<\/b> (2010) 157 (DOI: 10.1109\/tdmr.2009.2036719).","DOI":"10.1109\/TDMR.2009.2036719"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] J. Furuta, <i>et al<\/i>.: \u201cEvaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates,\u201d 2012 IEEE International Reliability Physics Symposium (IRPS) (2012) (DOI: 10.1109\/irps.2012.6241930).","DOI":"10.1109\/IRPS.2012.6241930"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Yanagawa, <i>et al.<\/i>: \u201cDirect test of SET pulse widths in 0.2-\u00b5m SOI logic cells irradiated by heavy ions,\u201d IEEE Trans. Nucl. Sci. <b>53<\/b> (2006) 3575 (DOI: 10.1109\/tns.2006.885110).","DOI":"10.1109\/TNS.2006.885110"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M. Ebara, <i>et al<\/i>.: \u201cProcess dependence of soft errors induced by alpha particles, heavy ions, and high energy neutrons on flip flops in FDSOI,\u201d IEEE J. Electron Devices Soc. <b>7<\/b> (2019) 817 (DOI: 10.1109\/jeds.2019.2907299).","DOI":"10.1109\/JEDS.2019.2907299"},{"key":"19","unstructured":"[19] S. Ganguly and S. Hojat: \u201cClock distribution design and verification for PowerPC microprocessors,\u201d Proc. IEEE International Conference on Computer Aided Design (ICCAD) (1995) 58 (DOI: 10.1109\/iccad.1995.479991)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] J. Furuta, <i>et al<\/i>.: \u201cMeasurement of neutron-induced SET pulse width using propagation-induced pulse shrinking,\u201d 2011 International Reliability Physics Symposium (2011) 5B.2.1 (DOI: 10.1109\/irps.2011.5784520).","DOI":"10.1109\/IRPS.2011.5784520"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] H. Sugisaki, <i>et al<\/i>.: \u201cFrequency dependency of soft error rates based on dynamic soft error tests,\u201d International Conference on IC Design and Technology (2023) (DOI: 10.1109\/icicdt59917.2023.10332341).","DOI":"10.1109\/ICICDT59917.2023.10332341"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] B. Nagesh and B.S.N. Chandra: \u201cDesignof efficient scan flip-flop,\u201d 2021 International Conference on Recent Trends on Electronics, Information, Communication &amp; Technology (RTEICT) (2021) 146 (DOI: 10.1109\/rteict52294.2021.9573924).","DOI":"10.1109\/RTEICT52294.2021.9573924"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] N.N. Mahatme, <i>et al<\/i>.: \u201cAnalysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies,\u201d 2010 IEEE International Reliability Physics Symposium (2010) 1031 (DOI: 10.1109\/irps.2010.5488680).","DOI":"10.1109\/IRPS.2010.5488680"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] H. Su, <i>et al<\/i>.: \u201cOptimal decoupling capacitor sizing and placement for standard-cell layout designs,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. <b>22<\/b> (2003) 428 (DOI: 10.1109\/tcad.2003.809658).","DOI":"10.1109\/TCAD.2003.809658"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] K.H. Safaryan: \u201cPower noise optimization with decoupling capacitors,\u201d 2017 IEEE East-West Design &amp; Test Symposium (EWDTS) (2017) (DOI: 10.1109\/ewdts.2017.8110121).","DOI":"10.1109\/EWDTS.2017.8110121"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] T. Olsson and P. Nilsson: \u201cA digitally controlled PLL for SoC applications,\u201d IEEE J. Solid-State Circuits <b>39<\/b> (2004) 751 (DOI: 10.1109\/jssc.2004.826333).","DOI":"10.1109\/JSSC.2004.826333"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Sugitani, <i>et al<\/i>.: \u201cRadiation hardened flip-flops with low area, delay and power overheads in a 65nm bulk process,\u201d 2023 IEEE International Reliability Physics Symposium (IRPS) (2023) (DOI: 10.1109\/irps48203.2023.10117957).","DOI":"10.1109\/IRPS48203.2023.10117957"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] M. Ebara, <i>et al<\/i>.: \u201cEvaluation of soft-error tolerance by neutrons and heavy ions on flip flops with guard gates in a 65-nm thin BOX FDSOI process,\u201d IEEE Trans. Nucl. Sci. <b>67<\/b> (2020) 1470 (DOI: 10.1109\/tns.2020.3002841).","DOI":"10.1109\/TNS.2020.3002841"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] J. Furuta, <i>et al<\/i>.: \u201cImpact of combinational logic delay for single event upset on flip flops in a 65nm FDSOI process,\u201d 2019 IEEE International Reliability Physics Symposium (IRPS) (2019) (DOI: 10.1109\/irps.2019.8720570).","DOI":"10.1109\/IRPS.2019.8720570"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] H. Asai, <i>et al<\/i>.: \u201cTerrestrial neutron-induced single-event burnout in SiC power diodes,\u201d 2011 12th European Conference on Radiation and Its Effects on Components and Systems (2011) 238 (DOI: 10.1109\/radecs.2011.6131401).","DOI":"10.1109\/RADECS.2011.6131401"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/13\/21_21.20240247\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,13]],"date-time":"2024-07-13T03:29:39Z","timestamp":1720841379000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/13\/21_21.20240247\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,10]]},"references-count":30,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240247","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,7,10]]},"article-number":"21.20240247"}}