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Luu, <i>et al<\/i>.: \u201cA 12-bit 300-MS\/s SAR ADC with inverter-based preamplifier and common-mode regulation DAC in 14-nm CMOS FinFET,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 3268 (DOI: 10.1109\/JSSC.2018.2862890).","DOI":"10.1109\/JSSC.2018.2862890"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] J. Luo, <i>et al<\/i>.: \u201cA 0.9-V 12-bit 100-MS\/s 14.6-fJ\/conversion-step SAR ADC in 40-nm CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>26<\/b> (2018) 1980 (DOI: 10.1109\/TVLSI.2018.2846746).","DOI":"10.1109\/TVLSI.2018.2846746"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] L. Scaletti, <i>et al<\/i>., \u201cA 10.2-ENOB, 150-MS\/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters,\u201d NEWCAS (2022) 978 (DOI: 10.1109\/NEWCAS52662.2022.9842195).","DOI":"10.1109\/NEWCAS52662.2022.9842195"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. 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