{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T14:32:19Z","timestamp":1772289139232,"version":"3.50.1"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"19","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,10,10]]},"DOI":"10.1587\/elex.21.20240457","type":"journal-article","created":{"date-parts":[[2024,8,22]],"date-time":"2024-08-22T22:11:45Z","timestamp":1724364705000},"page":"20240457-20240457","source":"Crossref","is-referenced-by-count":2,"title":["A 1.25-GS\/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity"],"prefix":"10.1587","volume":"21","author":[{"given":"Zeyu","family":"Li","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Guo","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanbo","family":"Jia","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinyu","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14bit 1GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/JSSC.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"2","unstructured":"[2] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14-bit 2.5GS\/s and 5GS\/s RF sampling ADC with background calibration and dither,\u201d VLSI (2016) 1 (DOI: 10.1109\/VLSIC.2016.7573537)."},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] F. Xu, <i>et al<\/i>.: \u201cA 12-bit 1-GS\/s pipelined ADC with a novel timing strategy in 40-nm CMOS process,\u201d MDPI Electron. <b>12<\/b> (2023) 924 (DOI: 10.3390\/electronics12040924).","DOI":"10.3390\/electronics12040924"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y.-Z. Xi, <i>et al<\/i>.: \u201cAn energy-efficient reconfigurable 18\/12-bit 1MS\/s pipelined-SAR ADC,\u201d AEU Int. J. Electron. Commun. <b>179<\/b> (2024) 155309 (DOI: 10.1016\/j.aeue.2024.155309).","DOI":"10.1016\/j.aeue.2024.155309"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] B. Vaz, <i>et al<\/i>.: \u201c16.1 A 13b 4GS\/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC,\u201d ISSCC (2017) 276 (DOI: 10.1109\/ISSCC.2017.7870368).","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] M. Chen, <i>et al<\/i>.: \u201cA 14bit 500MS\/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210171 (DOI: 10.1587\/elex.18.20210171).","DOI":"10.1587\/elex.18.20210171"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] C. Huang, <i>et al<\/i>.: \u201cAn input buffer with 85dB SFDR for high-speed pipeline ADC,\u201d ICTA (2022) 52 (DOI: 10.1109\/ICTA56932.2022.9962993).","DOI":"10.1109\/ICTA56932.2022.9962993"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Chen, <i>et al<\/i>.: \u201cA wide-band input buffer for 3GS\/s 12bit time-interleaved ADC,\u201d ICSICT (2016) 1467 (DOI: 10.1109\/ICSICT.2016.7998771).","DOI":"10.1109\/ICSICT.2016.7998771"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Z. Huang, <i>et al<\/i>.: \u201cLow-voltage high-linearity differential input buffer with current amplifier feed-forward compensation for high-speed ADCs,\u201d ICTA (2020) 41 (DOI: 10.1109\/ICTA50426.2020.9332138).","DOI":"10.1109\/ICTA50426.2020.9332138"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Z. Huang, <i>et al<\/i>.: \u201cA 6-GHz bandwidth input buffer based on AC-coupled flipped source follower for 12-bit 8-GS\/s ADC in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 4163 (DOI: 10.1109\/TCSII.2022.3188534).","DOI":"10.1109\/TCSII.2022.3188534"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] H. Rapakko and J. Kostamovaara: \u201cOn the performance and use of an improved source-follower buffer,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>54<\/b> (2007) 504 (DOI: 10.1109\/TCSI.2006.887609).","DOI":"10.1109\/TCSI.2006.887609"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] X. Guo, <i>et al<\/i>.: \u201cA 12-bit 2.32GS\/s pipelined\/SAR hybrid ADC with a high-linearity input buffer,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230369 (DOI: 10.1587\/elex.20.20230369).","DOI":"10.1587\/elex.20.20230369"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] C. Zhu, <i>et al<\/i>.: \u201cAnalysis and design of a large dither injection circuit for improving linearity in pipelined ADCs,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>27<\/b> (2019) 2008 (DOI: 10.1109\/TVLSI.2019.2912421).","DOI":"10.1109\/TVLSI.2019.2912421"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] T.C. Hung, <i>et al<\/i>.: \u201cA 12-bit time-interleaved 400-MS\/s pipelined ADC with split-ADC digital background calibration in 4,000 conversions\/channel,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>66<\/b> (2019) 1810 (DOI: 10.1109\/TCSII.2019.2895694).","DOI":"10.1109\/TCSII.2019.2895694"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] H.-S. Ku, <i>et al<\/i>.: \u201cA 87.5-dB-SNDR residue-integrated SAR ADC with a digital-domain capacitor mismatch calibration,\u201d JSTS J. Semiconductor Technology and Science <b>21<\/b> (2021) 143 (DOI: 10.5573\/jsts.2021.21.2.143).","DOI":"10.5573\/JSTS.2021.21.2.143"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] M.H. Naderi and J. Silva-Martinez: \u201cAlgorithmic-pipelined ADC with a modified residue curve for better linearity,\u201d MWSCAS (2017) 1446 (DOI: 10.1109\/MWSCAS.2017.8053205).","DOI":"10.1109\/MWSCAS.2017.8053205"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] B. Ding, <i>et al<\/i>.: \u201cA digital background calibration technique for interstage gain nonlinearity in pipelined ADCs,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20210571 (DOI: 10.1587\/elex.19.20210571).","DOI":"10.1587\/elex.19.20210571"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Y. Liu, <i>et al<\/i>.: \u201cA parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220084 (DOI: 10.1587\/elex.19.20220084).","DOI":"10.1587\/elex.19.20220084"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14-bit 125MS\/s IF\/RF sampling pipelined ADC with 100dB SFDR and 50fs jitter,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 1846 (DOI: 10.1109\/JSSC.2006.875291).","DOI":"10.1109\/JSSC.2006.875291"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] P. Yang, <i>et al<\/i>.: \u201cA 14-bit 200-Ms\/s SHA-less pipelined ADC with aperture error reduction,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>28<\/b> (2020) 2004 (DOI: 10.1109\/TVLSI.2020.3006147).","DOI":"10.1109\/TVLSI.2020.3006147"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] J. Lan, <i>et al<\/i>.: \u201cA single-channel 1.25-GS\/s 11-bit pipelined ADC with robust floating-powered ring amplifier and first-order gain error calibration,\u201d 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) (2022) 1 (DOI: 10.1109\/MWSCAS54063.2022.9859478).","DOI":"10.1109\/MWSCAS54063.2022.9859478"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] F. Cao, <i>et al<\/i>.: \u201cAn input buffer for 12bit 2GS\/s ADC,\u201d ASICON (2017) 750 (DOI: 10.1109\/ASICON.2017.8252584).","DOI":"10.1109\/ASICON.2017.8252584"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] T. Feng, <i>et al<\/i>.: \u201cA wideband high-linearity input buffer based on cascade complementary source follower,\u201d ICTA (2022) 13 (DOI: 10.1109\/ICTA56932.2022.9962966).","DOI":"10.1109\/ICTA56932.2022.9962966"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Li, <i>et al<\/i>.: \u201cWide-band input buffer with optimized linearity for high-speed high-resolution ADCs,\u201d ASID (2020) 116 (DOI: 10.1109\/ASID50160.2020.9271786).","DOI":"10.1109\/ASID50160.2020.9271786"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] S. Devarajan, <i>et al<\/i>.: \u201cA 12-b 10-GS\/s interleaved pipeline ADC in 28-nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 3204 (DOI: 10.1109\/JSSC.2017.2747758).","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] A.M.A. Ali, <i>et al<\/i>.: \u201cA 12-b 18-GS\/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 3210 (DOI: 10.1109\/JSSC.2020.3023882).","DOI":"10.1109\/JSSC.2020.3023882"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] L. Zhang, <i>et al<\/i>.: \u201cAn input buffer for 4GS\/s 14-b time-interleaved ADC,\u201d ASICON (2021) 1 (DOI: 10.1109\/ASICON52560.2021.9620387).","DOI":"10.1109\/ASICON52560.2021.9620387"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] L. Scaletti, <i>et al<\/i>.: \u201cA novel push-pull input buffer for wideband ADCs with improved high-frequency linearity,\u201d NEWCAS (2023) 1 (DOI: 10.1109\/NEWCAS57931.2023.10198057).","DOI":"10.1109\/NEWCAS57931.2023.10198057"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] J. Nan, <i>et al<\/i>.: \u201cAn 8-GHz bandwidth push-pull input buffer based on cascode source follower,\u201d ICCS (2023) 70 (DOI: 10.1109\/ICCS59502.2023.10367338).","DOI":"10.1109\/ICCS59502.2023.10367338"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] M.D. Matteis, <i>et al<\/i>.: \u201cA 33MHz 70dB-SNR super-source-follower-based low-pass analog filter,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 1516 (DOI: 10.1109\/JSSC.2015.2411626).","DOI":"10.1109\/JSSC.2015.2411626"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] Q. Yu, <i>et al<\/i>.: \u201cA 12b 8GS\/s time-interleaved 2b\/cycle pipelined-SAR ADC with layout-customized bootstrap and super- source-follower based open-loop residue amplifier,\u201d A-SSCC (2022) 1 (DOI: 10.1109\/A-SSCC56115.2022.9980717).","DOI":"10.1109\/A-SSCC56115.2022.9980717"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/19\/21_21.20240457\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,12]],"date-time":"2024-10-12T03:28:58Z","timestamp":1728703738000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/19\/21_21.20240457\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,10]]},"references-count":31,"journal-issue":{"issue":"19","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240457","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10,10]]},"article-number":"21.20240457"}}