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Eleventh European Conference on Computer Systems (2016) (DOI: 10.1145\/2901318.2901344).","DOI":"10.1145\/2901318.2901344"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Wu, <i>et al<\/i>.: \u201cUnimem: runtime data managementon non-volatile memory-based heterogeneous main memory,\u201d Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (2017) (DOI: 10.1145\/3126908.3126923).","DOI":"10.1145\/3126908.3126923"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] B.C. Lee, <i>et al<\/i>.: \u201cPhase-change technology and the future of main memory,\u201d IEEE Micro <b>30<\/b> (2010) 143 (DOI: 10.1109\/mm.2010.24).","DOI":"10.1109\/MM.2010.24"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S. Raoux, <i>et al<\/i>.: \u201cPhase-change random access memory: a scalable technology,\u201d IBM Journal of Research and Development <b>52<\/b> (2008) 465 (DOI: 10.1147\/rd.524.0465).","DOI":"10.1147\/rd.524.0465"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] H.-S.P. Wong, <i>et al<\/i>.: \u201cPhase change memory,\u201d Proc. IEEE <b>98<\/b>(2010) 2201 (DOI: 10.1109\/jproc.2010.2070050).","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] M. Le Gallo and A. Sebastian: \u201cAn overview of phase-change memory device physics,\u201d Journal of Physics D: Applied Physics <b>53<\/b> (2020) 213002 (DOI: 10.1088\/1361-6463\/ab7794).","DOI":"10.1088\/1361-6463\/ab7794"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Fujisaki: \u201cOverview of emerging semiconductor non-volatile memories,\u201d IEICE Electron. Express <b>9<\/b> (2012) 908 (DOI: 10.1587\/elex.9.908).","DOI":"10.1587\/elex.9.908"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] W. Xie, <i>et al<\/i>.: \u201cBlade-type phase-change random access memory technology, challenge and prospect,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230307 (DOI: 10.1587\/elex.20.20230307).","DOI":"10.1587\/elex.20.20230307"},{"key":"9","unstructured":"[9] S. Chen, <i>et al<\/i>.: \u201cRethinking database algorithms for phase change memory,\u201d 5th Biennial Conference on Innovative Data Systems Research, Conference Proceedings (2011)."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] P. Chi, <i>et al<\/i>.: \u201cAdapting B<sup>+<\/sup>-tree for emerging nonvolatile memory-based main memory,\u201d IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. <b>35<\/b> (2016) 1461 (DOI: 10.1109\/tcad.2015.2512899).","DOI":"10.1109\/TCAD.2015.2512899"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] P. Zhou, <i>et al<\/i>.: \u201cA durable and energy efficient main memory using phase change memory technology,\u201d Proc. 36th Annual International Symposium on Computer Architecture (2009) 14 (DOI: 10.1145\/1555754.1555759).","DOI":"10.1145\/1555754.1555759"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] P. Chi, <i>et al<\/i>.: \u201cMaking B<sup>+<\/sup>-tree efficient in PCM-based main memory,\u201d Proc. 2014 International Symposium on Low Power Electronics and Design (2014) 69 (DOI: 10.1145\/2627369.2627630).","DOI":"10.1145\/2627369.2627630"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S. Kargar and F. Nawab: \u201cChallenges and future directions for energy, latency, and lifetime improvements in nvms,\u201d Distributed and Parallel Databases <b>41<\/b> (2023) 163 (DOI: 10.1007\/s10619-022-07421-x).","DOI":"10.1007\/s10619-022-07421-x"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Shen, <i>et al<\/i>.: \u201cCharacterizing emerging heterogeneous memory,\u201d Proc. 2016 ACM SIGPLAN International Symposium on Memory Management (2016) 13 (DOI: 10.1145\/2926697.2926702).","DOI":"10.1145\/2926697.2926702"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Giardino, <i>et al<\/i>.: \u201cSoft2LM: application guided heterogeneous memory management,\u201d 2016 IEEE International Conference on Networking, Architecture and Storage (NAS) (2016) (DOI: 10.1109\/nas.2016.7549421).","DOI":"10.1109\/NAS.2016.7549421"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] F.X. Lin and X. Liu: \u201c<i>memif<\/i>: towards programming heterogeneous memory asynchronously,\u201d Proc. Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (2016) 369 (DOI: 10.1145\/2872362.2872401).","DOI":"10.1145\/2872362.2872401"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T.D. Doudali and A. Gavrilovska: \u201cCoMerge: toward efficient data placement in shared heterogeneous memory systems,\u201d Proc. International Symposium on Memory Systems (2017) 251 (DOI: 10.1145\/3132402.3132418).","DOI":"10.1145\/3132402.3132418"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] R. Lasch, <i>et al<\/i>.: \u201cCost modelling for optimal data placement in heterogeneous main memory,\u201d Proc. VLDB Endowment <b>15<\/b> (2022) 2867 (DOI: 10.14778\/3551793.3551837).","DOI":"10.14778\/3551793.3551837"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] L. Cui, <i>et al<\/i>.: \u201cSwapKV: a hotness aware in-memory key-value store for hybrid memory systems,\u201d IEEE Trans. Knowl. Data Eng. <b>35<\/b> (2021) 917 (DOI: 10.1109\/tkde.2021.3077264).","DOI":"10.1109\/TKDE.2021.3077264"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Liu, <i>et al<\/i>.: \u201cFast cacheline-based data replacement for hybrid DRAM and STT-MRAM main memory,\u201d IEICE Electron. Express <b>17<\/b> (2020) 20200090 (DOI: 10.1587\/elex.17.20200090).","DOI":"10.1587\/elex.17.20200090"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Sha, <i>et al<\/i>.: \u201cObject-oriented unified encrypted memory management for heterogeneous memory architectures,\u201d Proc. ACM on Management of Data <b>2<\/b> (2024) 1 (DOI: 10.1145\/3654958).","DOI":"10.1145\/3654958"},{"key":"22","unstructured":"[22] O. Kaiyrakhmet, <i>et al<\/i>.: \u201cSLM-DB: single-level key-value store with persistent memory,\u201d 17th USENIX Conference on File and Storage Technologies (2019)."},{"key":"23","unstructured":"[23] E. Doller: \u201cPhase change memory and its impacts on memory hierarchy\u201d(2009) http:\/\/www.pdl.cmu.edu\/SDI\/2009\/slides\/Numonyx.pdf."},{"key":"24","unstructured":"[24] Standard Performance Evaluation Corporation: http:\/\/www.spec.org."},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] M.K. Qureshi, <i>et al<\/i>.: \u201cScalable high performance main memory system using phase-change memory technology,\u201d Proc. 36th Annual International Symposium on Computer Architecture (2009) 24 (DOI: 10.1145\/1555754.1555760).","DOI":"10.1145\/1555754.1555760"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S. Lee, <i>et al<\/i>.: \u201cCLOCK-DWF: a write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures,\u201d IEEE Trans. Comput. <b>63<\/b> (2014) 2187 (DOI: 10.1109\/tc.2013.98).","DOI":"10.1109\/TC.2013.98"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] L.E. Ramos, <i>et al<\/i>.: \u201cPage placement in hybrid memory systems,\u201d Proc. International Conference on Supercomputing (2011) 85 (DOI: 10.1145\/1995896.1995911).","DOI":"10.1145\/1995896.1995911"},{"key":"28","unstructured":"[28] The LLVM Compiler Infrastructure: http:\/\/llvm.org\/."},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H. Volos, <i>et al<\/i>.: \u201cQuartz: a lightweight performance emulator for persistent memory software,\u201d Proc. 16th Annual Middleware Conference (2015) 37 (DOI: 10.1145\/2814576.2814806).","DOI":"10.1145\/2814576.2814806"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] J. Huang, <i>et al<\/i>.: \u201cNVRAM-aware logging in transaction systems,\u201d Proc. VLDB Endowment <b>8<\/b> (2014) 389 (DOI: 10.14778\/2735496.2735502).","DOI":"10.14778\/2735496.2735502"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] W.-H. Kim, <i>et al<\/i>.: \u201cNVWAL: exploiting NVRAM in write-ahead logging,\u201d ACM SIGPLAN Notices <b>51<\/b> (2016) 385 (DOI: 10.1145\/2954679.2872392).","DOI":"10.1145\/2954679.2872392"},{"key":"32","unstructured":"[32] S.K. Lee, <i>et al<\/i>.: \u201cWORT: write optimal radix tree for persistent memory storage systems,\u201d 15th USENIX Conference on File and Storage Technologies (2017) 257."},{"key":"33","unstructured":"[33] A.C. De Melo: \u201cThe new Linux \u2018perf\u2019 tools,\u201d Slides from Linux Kongress <b>18<\/b> (2010) 1."},{"key":"34","doi-asserted-by":"crossref","unstructured":"[34] S. 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