{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,28]],"date-time":"2024-12-28T05:22:02Z","timestamp":1735363322992,"version":"3.32.0"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"24","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2024,12,25]]},"DOI":"10.1587\/elex.21.20240577","type":"journal-article","created":{"date-parts":[[2024,11,13]],"date-time":"2024-11-13T22:13:04Z","timestamp":1731535984000},"page":"20240577-20240577","source":"Crossref","is-referenced-by-count":0,"title":["A hybrid interface design based on chip edge connection and inductively coupling connection for 3D stacked chips"],"prefix":"10.1587","volume":"21","author":[{"given":"Zhuo","family":"Yang","sequence":"first","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Cui","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Xiong","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pan","family":"Zheng","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Gao","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenwen","family":"Cai","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hui","family":"Lv","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Zhang","sequence":"additional","affiliation":[{"name":"Hubei University of Technology"},{"name":"National \u201c111 Research Center for Microeletronics and Integrated Circuits\u201d"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] F.-C. Hsu, <i>et al<\/i>.: \u201c3D heterogeneous integration with multiple stacking fan-out package,\u201d IEEE ECTC (2018) 337 (DOI: 10.1109\/ECTC.2018.00058).","DOI":"10.1109\/ECTC.2018.00058"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] V. Pagracious, <i>et al<\/i>.: \u201c3D-cool: design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip,\u201d IEEE COOL CHIPS (2018) 1 (DOI: 10.1109\/CoolChips.2018.8373074).","DOI":"10.1109\/CoolChips.2018.8373074"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] E.J. Marinissen, <i>et al<\/i>.: \u201cA structured and scalable test access architecture for TSV-based 3D stacked ICs,\u201d IEEE VTS (2010) 269 (DOI: 10.1109\/vts.2010.5469556).","DOI":"10.1109\/VTS.2010.5469556"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] L. 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Pandey and A. Sahu: \u201cPerformance and area trade-off of 3D-stacked DRAM based chip multiprocessor with hybrid interconnect,\u201d IEEE Trans. Emerg. Topics Comput. <b>9<\/b> (2021) 1945 (DOI: 10.1109\/TETC.2019.2946887).","DOI":"10.1109\/TETC.2019.2946887"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Hernandez, <i>et al<\/i>.: \u201cFault-tolerant vertical link design for effective 3D stacking,\u201d IEEE Comput. Archit. Lett. <b>10<\/b> (2011) 41 (DOI: 10.1109\/L-CA.2011.17).","DOI":"10.1109\/L-CA.2011.17"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Saito, <i>et al<\/i>.: \u201cA 2Gb\/s 1.8pJ\/b\/chip inductive-coupling through-chip bus for 128-Die NAND-flash memory stacking,\u201d IEEE ISSCC (2010) 440 (DOI: 10.1109\/isscc.2010.5433929).","DOI":"10.1109\/ISSCC.2010.5433929"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] Y. 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Papatryfonos, <i>et al<\/i>.: \u201cCo-package technology platform for low-power and low-cost data centers,\u201d Applied Sciences <b>11<\/b> (2021) 6098 (DOI: 10.3390\/app11136098).","DOI":"10.3390\/app11136098"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/24\/21_21.20240577\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,28]],"date-time":"2024-12-28T03:29:11Z","timestamp":1735356551000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/21\/24\/21_21.20240577\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,25]]},"references-count":30,"journal-issue":{"issue":"24","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240577","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2024,12,25]]},"article-number":"21.20240577"}}