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Hayes, <i>et al<\/i>.: \u201cDesign of robust digitally controlled DC-DC converters in the presence of strong interference,\u201d International Journal of Circuit Theory and Applications <b>45<\/b> (2017) 1742 (DOI: 10.1002\/cta.2351).","DOI":"10.1002\/cta.2351"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Ahmad and B. Bakkaloglu: \u201cA digitally controlled DC-DC buck converter using frequency domain ADCs,\u201d 2010 Twenty-fifth annual IEEE applied power electronics conference and exposition (APEC) (2010) 1871 (DOI: 10.1109\/APEC.2010.5433488).","DOI":"10.1109\/APEC.2010.5433488"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] F. Kuttner, <i>et al<\/i>.: \u201cA digitally controlled DC-DC converter for SoC in 28\u2006nm CMOS,\u201d 2011 IEEE International Solid-State Circuits Conference (2011) 384 (DOI: 10.1109\/ISSCC.2011.5746364).","DOI":"10.1109\/ISSCC.2011.5746364"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] V. Vindhya and V. Reddy: \u201cPID-Fuzzy logic hybrid controller for a digitally controlled DC-DC converter,\u201d 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE) (2013) 362 (DOI: 10.1109\/ICGCE.2013.6823461).","DOI":"10.1109\/ICGCE.2013.6823461"},{"key":"5","doi-asserted-by":"publisher","unstructured":"[5] F. Kurokawa, <i>et al<\/i>.: \u201cA reference modification model digitally controlled DC-DC converter for improvement of transient response,\u201d IEEE Trans. Power Electron. <b>31<\/b> (2015) 871 (DOI: 10.1109\/TPEL.2015.2411679)","DOI":"10.1109\/TPEL.2015.2411679"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Sumita and T. Sato: \u201cPID control method using predicted output voltage for digitally controlled DC\/DC converter,\u201d 2019 1st International Conference on Electrical, Control and Instrumentation Engineering (ICECIE) (2019) 1 (DOI: 10.1109\/ICECIE47765.2019.8974779)","DOI":"10.1109\/ICECIE47765.2019.8974779"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Usmonov, P.S. Crovetti, F. Gregoretti, <i>et al<\/i>.: \u201cSuppression of quantization-induced limit cycles in digitally controlled DC-DC converters by dyadic digital pulse width modulation,\u201d 2019 IEEE Energy Conversion Congress and Exposition (ECCE) (2019) 2224 (DOI: 10.1109\/ECCE.2019.8913214).","DOI":"10.1109\/ECCE.2019.8913214"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] S.S. Kudva and R. Harjani: \u201cFully integrated capacitive DC-DC converter with all-digital ripple mitigation technique,\u201d IEEE J. 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Topics Power Electron. <b>9<\/b> (2020) 1205 (DOI: 10.1109\/JESTPE.2020.2978064).","DOI":"10.1109\/JESTPE.2020.2978064"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] G. Zhou, <i>et al<\/i>.: \u201cDigital average voltage\/digital average current predictive control for switching DC-DC converters,\u201d IEEE J. Emerg. Sel. Topics Power Electron. <b>6<\/b> (2018) 1819 (DOI: 10.1109\/JESTPE.2018.2868974).","DOI":"10.1109\/JESTPE.2018.2868974"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] E. Mart\u00ed-Arbona, <i>et al<\/i>.: \u201cA high-voltage-compliant current-to-digital sensor for DC-DC converters in standard CMOS technology,\u201d IEEE Trans. Power Electron. <b>32<\/b> (2016) 2180 (DOI: 10.1109\/TPEL.2016.2562108).","DOI":"10.1109\/TPEL.2016.2562108"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. Buso and T. Caldognetto: \u201cA nonlinear wide-bandwidth digital current controller for DC-DC and DC-AC converters,\u201d IEEE Trans. Ind. Electron. <b>62<\/b> (2015) 7687 (DOI: 10.1109\/TIE.2015.2465351).","DOI":"10.1109\/TIE.2015.2465351"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Palermo, <i>et al<\/i>.: \u201cAnalog-to-digital converter-based serial links: An overview,\u201d IEEE Solid-State Circuits Mag. <b>10<\/b> (2018) 35 (DOI: 10.1109\/MSSC.2018.2844603).","DOI":"10.1109\/MSSC.2018.2844603"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] H. Jiang, <i>et al<\/i>.: \u201cAnalog-to-digital converter design exploration for compute-in-memory accelerators,\u201d IEEE Des. Test <b>39<\/b> (2021) 48 (DOI: 10.1109\/MDAT.2021.3050715).","DOI":"10.1109\/MDAT.2021.3050715"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T.J. Kutre, <i>et al<\/i>.: \u201cAdvanced architecture of analog to digital converter derived from half flash ADC,\u201d Distributed Computing and Optimization Techniques: Select Proceedings of ICDCOT 2021 (2022) 141 (DOI: 10.1007\/978-981-19-2281-7_14).","DOI":"10.1007\/978-981-19-2281-7_14"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] A. Rezapour, <i>et al<\/i>.: \u201cA new approach for 10-bit pipeline analog-to-digital converter design based on 0.18\u2006<i>\u03bc<\/i>m CMOS technology,\u201d AEU-International Journal of Electronics and Communications <b>99<\/b> (2019) 299 (DOI: 10.1016\/j.aeue.2018.10.030).","DOI":"10.1016\/j.aeue.2018.10.030"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] O. Ordentlich, <i>et al<\/i>.: \u201cA modulo-based architecture for analog-to-digital conversion,\u201d IEEE J. Sel. Topics Signal Process. <b>12<\/b> (2018) 825 (DOI: 10.1109\/JSTSP.2018.2863189).","DOI":"10.1109\/JSTSP.2018.2863189"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Z. Zhou, <i>et al<\/i>.: \u201cA 12\u2006bit 120\u2006MS\/s SHA-less pipeline ADC with capacitor mismatch error calibration,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180481 (DOI: 10.1587\/elex.15.20180481).","DOI":"10.1587\/elex.15.20180481"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] D. Xu, <i>et al<\/i>.: \u201cA 10-bit 1.2\u2006GS\/s 45\u2006mW time-interleaved SAR ADC with background calibration,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20171235 (DOI: 10.1587\/elex.15.20171235).","DOI":"10.1587\/elex.15.20171235"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] H.Y. Lee, <i>et al<\/i>.: \u201c500\u2006MS\/s 4-bit flash ADC with complementary architecture,\u201d Journal of Electromagnetic Engineering and Science <b>24<\/b> (2024) 98 (DOI: 10.26866\/jees.2024.1.r.209).","DOI":"10.26866\/jees.2024.1.r.209"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] I.M. Yi, <i>et al<\/i>.: \u201cA 15.1-mW 6-GS\/s 6-bit single-channel flash ADC with selectively activated 8\u00d7 time-domain latch interpolation,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2020) 455 (DOI: 10.1109\/JSSC.2020.3017229).","DOI":"10.1109\/JSSC.2020.3017229"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] D. Mohammadi, <i>et al<\/i>.: \u201cA 7-GS\/s 5-bit continuous-time pipelined binary-search flash ADC in 28-nm CMOS,\u201d IEEE Solid-State Circuits Lett. <b>3<\/b> (2020) 366 (DOI: 10.1109\/LSSC.2020.3023030).","DOI":"10.1109\/LSSC.2020.3023030"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] M.M. Hossain, <i>et al<\/i>.: \u201cOptimal design method of sub-ranging ADC based on stochastic comparator,\u201d IEICE Trans. Fundamentals <b>E101-A<\/b> (2018) 410 (DOI: 10.1587\/transfun.E101.A.410)","DOI":"10.1587\/transfun.E101.A.410"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] H. Ham, <i>et al<\/i>.: \u201cDesign of a high-speed-sampling stochastic flash analog-to-digital converter using device mismatch,\u201d Electronics and Communications in Japan <b>96<\/b> (2013) 51 (DOI: 10.1002\/ecj.11411).","DOI":"10.1002\/ecj.11411"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] W.J. Yun, <i>et al<\/i>.: \u201cA 4-bit 2\u2006GSamples\/s parallel flash ADC using comb-type reference ladder,\u201d IEICE Electron. Express <b>5<\/b> (2008) 562 (DOI: 10.1587\/elex.5.562).","DOI":"10.1587\/elex.5.562"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] X. Zou and S. Nakatake: \u201cA low voltage stochastic flash ADC without comparator,\u201d IEICE Trans. Fundamentals <b>E102-A<\/b> (2019) 886 (DOI: 10.1587\/transfun.E102.A.886).","DOI":"10.1587\/transfun.E102.A.886"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] T. Kitamura, <i>et al<\/i>.: \u201cOrder statistics based low-power flash ADC with on-chip comparator selection.\u201d IEICE Trans. Fundamentals <b>E105-A<\/b> (2022) 1450 (DOI: 10.1587\/transfun.2021KEP0007).","DOI":"10.1587\/transfun.2021KEP0007"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] G.M. Sung, <i>et al<\/i>.: \u201cA third-order multibit switched-current delta-sigma modulator with switched-capacitor flash ADC and IDWA,\u201d IEICE Trans. Electron. <b>E100-C<\/b> (2017) 684 (DOI: 10.1587\/transele.E100.C.684).","DOI":"10.1587\/transele.E100.C.684"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] T. Kitamura, <i>et al<\/i>.: \u201cDesign of reference-free flash ADC with on-chip rank-based comparator selection using multiple comparator groups,\u201d IPSJ Transactions on System and LSI Design Methodology <b>17<\/b> (2024) 36 (DOI: 10.2197\/ipsjtsldm.17.36).","DOI":"10.2197\/ipsjtsldm.17.36"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] X. Guo, <i>et al<\/i>.: \u201cA 12-bit 2.32\u2006GS\/s pipelined\/SAR hybrid ADC with a high-linearity input buffer,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230369 (DOI: 10.1587\/elex.20.20230369).","DOI":"10.1587\/elex.20.20230369"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/3\/22_21.20240628\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,15]],"date-time":"2025-02-15T03:28:10Z","timestamp":1739590090000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/3\/22_21.20240628\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,10]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.21.20240628","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2,10]]},"article-number":"21.20240628"}}