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Ren, <i>et al.<\/i>: \u201cSemi-conductor pillars in 5G era and beyond,\u201d 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2022) 8 (DOI: 10.1109\/A-SSCC56115.2022.9980537).","DOI":"10.1109\/A-SSCC56115.2022.9980537"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Ma, <i>et al.<\/i>: \u201cA case study of testing strategy for AI SoC,\u201d 2019 IEEE International Test Conference in Asia (ITC-Asia) (2019) 61 (DOI: 10.1109\/ITC-Asia.2019.00024).","DOI":"10.1109\/ITC-Asia.2019.00024"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Wu, <i>et al.<\/i>: \u201cAn efficient design framework for 2\u00d72 CNN accelerator chiplet cluster with SerDes interconnects,\u201d 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS) (2023) 11 (DOI: 10.1109\/AICAS57966.2023.10168573).","DOI":"10.1109\/AICAS57966.2023.10168573"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] K. 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Sun, <i>et al.<\/i>: \u201cA 16\u2006Gb\/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS,\u201d Microelectronics Journal <b>148<\/b> (2024) 106216 (DOI: 10.1016\/j.mejo.2024.106216).","DOI":"10.1016\/j.mejo.2024.106216"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] P.A. Francese, <i>et al.<\/i>: \u201cA 50\u2006GB\/S 1.6\u2006PJ\/B RX data-path with quarter-rate 3-tap speculative DFE,\u201d 2018 IEEE Symposium on VLSI Circuits (2018) 267 (DOI: 10.1109\/VLSIC.2018.8502359).","DOI":"10.1109\/VLSIC.2018.8502359"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] D. Lee, <i>et al.<\/i>: \u201cA 10.8\u2006Gb\/s quarter-rate 1 FIR 1 IIR direct DFE with non-time-overlapping data generation for 4:1 CMOS clockless multiplexer,\u201d IEEE Trans. Circuits Syst. II, Exp. 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