{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,13]],"date-time":"2025-04-13T04:05:24Z","timestamp":1744517124843,"version":"3.40.4"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,4,10]]},"DOI":"10.1587\/elex.22.20240601","type":"journal-article","created":{"date-parts":[[2025,2,18]],"date-time":"2025-02-18T22:11:42Z","timestamp":1739916702000},"page":"20240601-20240601","source":"Crossref","is-referenced-by-count":0,"title":["A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability"],"prefix":"10.1587","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-1697-6556","authenticated-orcid":false,"given":"Rongfeng","family":"Li","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xueming","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chaoming","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xianghong","family":"Hu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuanmiao","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shansen","family":"Fu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongmin","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Guangdong Polytechnic Normal University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuting","family":"Cai","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoming","family":"Xiong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] K. Simonyan and A. Zisserman: \u201cVery deep convolutional networks for large-scale image recognition,\u201d Computer Science (2014)."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. He, <i>et al<\/i>.: \u201cDeep residual learning for image recognition,\u201d 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) (2016) 770 (DOI: 10.1109\/CVPR.2016.90).","DOI":"10.1109\/CVPR.2016.90"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Q. Cheng, <i>et al<\/i>.: \u201cA low-power sparse convolutional neural network accelerator with pre-encoding radix-4 booth multiplier,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>70<\/b> (2023) 2246 (DOI: 10.1109\/TCSII.2022.3231361).","DOI":"10.1109\/TCSII.2022.3231361"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Y. Xu, <i>et al<\/i>.: \u201cDesign and implementation of an efficient CNN accelerator for low-cost FPGAs,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220370 (DOI: 10.1587\/elex.19.20220370).","DOI":"10.1587\/elex.19.20220370"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Moon, <i>et al<\/i>.: \u201cA 127.8\u2006TOPS\/W arbitrarily quantized 1-to-8b scalable-precision accelerator for general-purpose deep learning with reduction of storage, logic and latency waste,\u201d 2023 IEEE International Solid-State Circuits Conference (ISSCC) (2023) 21 (DOI: 10.1109\/ISSCC42615.2023.10067615).","DOI":"10.1109\/ISSCC42615.2023.10067615"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] F. Liu, <i>et al<\/i>.: \u201cCASSANN-V2: a high-performance cnn accelerator architecture with on-chip memory self-adaptive tuning,\u201d IEICE Electronics Express <b>19<\/b> (2022) 20220124 (DOI: 10.1587\/elex.19.20220124).","DOI":"10.1587\/elex.19.20220124"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] E. Wang, <i>et al<\/i>.: \u201cLUTNet: learning FPGA configurations for highly efficient neural network inference,\u201d IEEE Trans. Comput. <b>69<\/b> (2020) 1795 (DOI: 10.1109\/TC.2020.2978817).","DOI":"10.1109\/TC.2020.2978817"},{"key":"8","unstructured":"[8] S. Zhou, <i>et al<\/i>.: \u201cDoReFa-Net: Training low bitwidth convolutional neural networks with low bitwidth gradients,\u201d arXiv preprint (2018) https:\/\/arxiv.org\/abs\/1606.06160."},{"key":"9","unstructured":"[9] J. Choi, <i>et al<\/i>.: \u201cPACT: parameterized clipping activation for quantized neural networks,\u201d arXiv preprint (2018) https:\/\/arxiv.org\/abs\/1805.06085."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] X. Hu, <i>et al<\/i>.: \u201cTiNNA: a tiny accelerator for neural networks with efficient DSP optimization,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 2301 (DOI: 10.1109\/TCSII.2022.3150980).","DOI":"10.1109\/TCSII.2022.3150980"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] X. Hu, <i>et al<\/i>.: \u201cA tiny accelerator for mixed-bit sparse CNN based on efficient fetch method of SIMO SPad,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>70<\/b> (2023) 3079 (DOI: 10.1109\/TCSII.2023.3257298).","DOI":"10.1109\/TCSII.2023.3257298"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Guo, <i>et al<\/i>.: \u201cBit-width adaptive accelerator design for convolution neural network,\u201d 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (2018) 1 (DOI: 10.1109\/ISCAS.2018.8351666).","DOI":"10.1109\/ISCAS.2018.8351666"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] H. Sharma, <i>et al<\/i>.: \u201cBit fusion: bit-level dynamically composable architecture for accelerating deep neural network,\u201d 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) (2018) 764 (DOI: 10.1109\/ISCA.2018.00069).","DOI":"10.1109\/ISCA.2018.00069"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] W. Liu, <i>et al<\/i>.: \u201cA precision-scalable energy-efficient convolutional neural network accelerator,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 3484 (DOI: 10.1109\/TCSI.2020.2993051).","DOI":"10.1109\/TCSI.2020.2993051"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Ryu, <i>et al<\/i>.: \u201cBitBlade: energy-efficient variable bit-precision hardware accelerator for quantized neural networks,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 1924 (DOI: 10.1109\/JSSC.2022.3141050).","DOI":"10.1109\/JSSC.2022.3141050"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] W. Li, <i>et al<\/i>.: \u201cLow-complexity precision-scalable multiply-accumulate unit architectures for deep neural network accelerators,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>70<\/b> (2023) 1610 (DOI: 10.1109\/TCSII.2022.3231418).","DOI":"10.1109\/TCSII.2022.3231418"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] W. Li, <i>et al<\/i>.: \u201cA precision-scalable deep neural network accelerator with activation sparsity exploitation,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. <b>43<\/b> (2024) 263 (DOI: 10.1109\/TCAD.2023.3310916).","DOI":"10.1109\/TCAD.2023.3310916"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] X. Zhou, <i>et al<\/i>.: \u201cA convolutional neural network accelerator architecture with fine-granular mixed precision configurability,\u201d 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (2020) 1 (DOI: 10.1109\/ISCAS45731.2020.9180844).","DOI":"10.1109\/ISCAS45731.2020.9180844"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S. He, <i>et al<\/i>.: \u201cBit-offsetter: a bit-serial DNN accelerator with weight-offset mac for bit-wise sparsity exploitation,\u201d 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS) (2023) 1 (DOI: 10.1109\/AICAS57966.2023.10168618).","DOI":"10.1109\/AICAS57966.2023.10168618"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] T. Yang, <i>et al<\/i>.: \u201cA winograd-based CNN accelerator with a fine-grained regular sparsity pattern,\u201d 2020 30th International Conference on Field-Programmable Logic and Applications (FPL) (2020) 254 (DOI: 10.1109\/FPL50879.2020.00050).","DOI":"10.1109\/FPL50879.2020.00050"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] T. Yang, <i>et al<\/i>.: \u201cBISWSRBS: a winograd-based CNN accelerator with a fine-grained regular sparsity pattern and mixed precision quantization,\u201d ACM Trans. Reconfigurable Technol. Syst. <b>14<\/b> (2021) 1 (DOI: 10.1145\/3467476).","DOI":"10.1145\/3467476"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] Y.-H. Chen, <i>et al<\/i>.: \u201cEyeriss v2: a flexible accelerator for emerging deep neural networks on mobile devices,\u201d IEEE J. Emerg. Sel. Topics Circuits Syst. <b>9<\/b> (2019) 292 (DOI: 10.1109\/JETCAS.2019.2910232).","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] Y.-H. Chen, <i>et al<\/i>.: \u201cEyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 127 (DOI: 10.1109\/JSSC.2016.2616357).","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] X. Zhao, <i>et al<\/i>.: \u201cBitPruner: network pruning for bit-serial accelerators,\u201d 2020 57th ACM\/IEEE Design Automation Conference (DAC) (2020) 1 (DOI: 10.1109\/DAC18072.2020.9218534).","DOI":"10.1109\/DAC18072.2020.9218534"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] M. Shi, <i>et al<\/i>.: \u201cBitWave: exploiting column-based bit-level sparsity for deep learning acceleration,\u201d 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (2024) 732 (DOI: 10.1109\/HPCA57654.2024.00062).","DOI":"10.1109\/HPCA57654.2024.00062"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] H. An, <i>et al<\/i>.: \u201c29.3 an 8.09\u2006TOPS\/W neural engine leveraging bit-sparsified sign-magnitude multiplications and dual adder trees,\u201d 2023 IEEE International Solid-State Circuits Conference (ISSCC) (2023) 422 (DOI: 10.1109\/ISSCC42615.2023.10067269).","DOI":"10.1109\/ISSCC42615.2023.10067269"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] S. Yang, <i>et al<\/i>.: \u201cLane shared bit-pragmatic deep neural network computing architecture and circuit,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 486 (DOI: 10.1109\/TCSII.2020.3007983).","DOI":"10.1109\/TCSII.2020.3007983"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Albericio, <i>et al<\/i>.: \u201cBit-pragmatic deep neural network computing,\u201d 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO) (2017) 382 (DOI: 10.1145\/3123939.3123982).","DOI":"10.1145\/3123939.3123982"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] M. Huang, <i>et al<\/i>.: \u201cA high performance multi-bit-width booth vector systolic accelerator for nas optimized deep learning neural networks,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 3619 (DOI: 10.1109\/TCSI.2022.3178474).","DOI":"10.1109\/TCSI.2022.3178474"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Y. Meng, <i>et al<\/i>.: \u201cALSCA: a large-scale sparse CNN accelerator using position-first dataflow and input channel merging approach,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 3473 (DOI: 10.1109\/TCSII.2024.3359263).","DOI":"10.1109\/TCSII.2024.3359263"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/7\/22_22.20240601\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T04:20:29Z","timestamp":1744431629000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/7\/22_22.20240601\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,10]]},"references-count":30,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20240601","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,4,10]]},"article-number":"22.20240601"}}