{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T05:31:09Z","timestamp":1741411869564,"version":"3.38.0"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,3,10]]},"DOI":"10.1587\/elex.22.20240726","type":"journal-article","created":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T22:11:45Z","timestamp":1737497505000},"page":"20240726-20240726","source":"Crossref","is-referenced-by-count":0,"title":["A dither-based background calibration circuit for pipelined ADCs in 40\u2006nm CMOS"],"prefix":"10.1587","volume":"22","author":[{"given":"Ben","family":"He","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Guo","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanbo","family":"Jia","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai","family":"Sun","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Zhou","sequence":"additional","affiliation":[{"name":"Acela Microelectronics, Co., Ltd."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhijie","family":"Chen","sequence":"additional","affiliation":[{"name":"Beijing University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinyu","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] B. Hershberg, <i>et al.<\/i>: \u201cAsynchronous event-driven clocking and control in pipelined ADCs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 2813 (DOI: 10.1109\/TCSI.2021.3077881).","DOI":"10.1109\/TCSI.2021.3077881"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K.-J. Moon, <i>et al.<\/i>: \u201cA 28-nm CMOS 12-bit 250-MS\/s voltage-current-time domain 3-stage pipelined ADC,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 2843 (DOI: 10.1109\/TCSII.2020.2990910).","DOI":"10.1109\/TCSII.2020.2990910"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Liu, <i>et al.<\/i>: \u201cA parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220084 (DOI: 10.1587\/ELEX.19.20220084).","DOI":"10.1587\/elex.19.20220084"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] R. Mittal, <i>et al.<\/i>: \u201cA 6.4-GS\/s 1-GHz BW continuous-time pipelined ADC with time-interleaved sub-ADC-DAC achieving 61.7-dB SNDR in 16-nm FinFET,\u201d Symp. VLSI Circuits Dig. Tech. Papers (2023) 1 (DOI: 10.23919\/vlsitechnologyandcir57934.2023.10185279).","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185279"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J.-H. Chung, <i>et al.<\/i>: \u201cAn 81.2\u2006dB-SNDR dual-residue pipeline ADC with a 2nd-order noise-shaping interpolating SAR ADC,\u201d Proc. IEEE Custom Integr. Circuits Conf. (2023) 1 (DOI: 10.1109\/CICC57935.2023.10121247).","DOI":"10.1109\/CICC57935.2023.10121247"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] M. Chen, <i>et al.<\/i>: \u201cA 14\u2006bit 500\u2006MS\/s 85.62\u2006dBc SFDR 66.29\u2006dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40\u2006nm CMOS,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210171 (DOI: 10.1587\/ELEX.18.20210171).","DOI":"10.1587\/elex.18.20210171"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] X. Zhou, <i>et al.<\/i>: \u201cA 3.3\u2006V 14-bit 125\u2006MS\/s pipeline ADC with hybrid 1.8\u2006V\/3.3\u2006V MOSFET technique in 0.18\u2006<i>\u03bc<\/i>m CMOS,\u201d IEICE Electron. Express <b>21<\/b> (2024) 20240038 (DOI: 10.1587\/ELEX.21.20240038).","DOI":"10.1587\/elex.21.20240038"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] K. Yamashita, <i>et al.<\/i>: \u201cA 4.6K to 400K functional PVT-robust ringamp-based 250\u2006MS\/s 12b pipelined ADC with pole-aware bias calibration,\u201d 2023 IEEE Custom Integrated Circuits Conference (CICC) 1 (DOI: 10.1109\/CICC57935.2023.10121320).","DOI":"10.1109\/CICC57935.2023.10121320"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T.-C. Hung and T.-H. Kuo: \u201cA 4.86\u2006mW 15-bit 22.5\u2006MS\/s pipelined ADC with 74\u2006dB SNDR in 90\u2006nm CMOS using averaging correlated level shifting technique,\u201d ASSCC Dig. Tech. Papers (2016) 161 (DOI: 10.1109\/ASSCC.2016.7844160).","DOI":"10.1109\/ASSCC.2016.7844160"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Z. Zhou, <i>et al.<\/i>: \u201cA 12\u2006bit 120\u2006MS\/s SHA-less pipeline ADC with capacitor mismatch error calibration,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180481 (DOI: 10.1587\/ELEX.15.20180481).","DOI":"10.1587\/elex.15.20180481"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Chatterjee and S. Roy: \u201cA self-calibration method of a pipeline ADC based on dynamic capacitance allotment,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>30<\/b> (2022) 666 (DOI: 10.1109\/TVLSI.2022.3151479).","DOI":"10.1109\/TVLSI.2022.3151479"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. 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Liu, <i>et al.<\/i>: \u201cA dual-supply two-stage CMOS Op-amp for high-speed pipeline ADCs application,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 650 (DOI: 10.1109\/TCSII.2019.2926133).","DOI":"10.1109\/TCSII.2019.2926133"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] M. Ni, <i>et al.<\/i>: \u201cA 13-Bit 2-GS\/s time-interleaved ADC with improved correlation-based timing skew calibration strategy,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 481 (DOI: 10.1109\/TCSI.2021.3122984).","DOI":"10.1109\/TCSI.2021.3122984"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] M. El-Chammas, <i>et al.<\/i>: \u201c15.8 90\u2006dB-SFDR 14b 500\u2006MS\/S BiCMOS switched-current pipelined ADC,\u201d ISSCC Dig. Tech. Papers (2015) 1 (DOI: 10.1109\/ISSCC.2015.7063038).","DOI":"10.1109\/ISSCC.2015.7063038"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C. 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Papers (2000) 42 (DOI: 10.1109\/ISSCC.2000.839683).","DOI":"10.1109\/ISSCC.2000.839683"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] E. Siragusa and I. Galton: \u201cA digitally enhanced 1.8-V 15-bit 40-MSample\/s CMOS pipelined ADC,\u201d IEEE J. Solid-State Circuits <b>39<\/b> (2004) 2126 (DOI: 10.1109\/JSSC.2004.836230).","DOI":"10.1109\/JSSC.2004.836230"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] A.M.A. Ali, <i>et al.<\/i>: \u201cA 14\u2006bit 1\u2006GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/JSSC.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] M. Liu, <i>et al.<\/i>: \u201cPN-assisted digital background calibration of two-step ADC to over 14-bit accuracy,\u201d Analog Integr. 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(2006) 1156 (DOI: 10.1109\/IMTC.2006.328420).","DOI":"10.1109\/IMTC.2006.328420"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] H. Pan and A. Abidi: \u201cSpectral spurs due to quantization in Nyquist ADCs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>51<\/b> (2004) 1422 (DOI: 10.1109\/TCSI.2004.832755).","DOI":"10.1109\/TCSI.2004.832755"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/5\/22_22.20240726\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T03:27:00Z","timestamp":1741404420000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/5\/22_22.20240726\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,10]]},"references-count":31,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20240726","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,3,10]]},"article-number":"22.20240726"}}