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Chang, <i>et al.<\/i>: \u201cA 28\u2006nm 256\u2006kb 6T-SRAM with 280\u2006mV improvement in VMIN using a dual-split-control assist scheme,\u201d IEEE International Solid-State Circuits Conference (2015) (DOI: 10.1109\/ISSCC.2015.7063052).","DOI":"10.1109\/ISSCC.2015.7063052"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] T. Fukuda, <i>et al.<\/i>: \u201cA 7\u2006ns-access-time 25\u2006uW\/MHz 128\u2006kb SRAM for low-power fast wake-up MCU in 65\u2006nm CMOS with 27\u2006fA\/b retention current,\u201d IEEE International Solid-State Circuits Conference (2014) (DOI: 10.1109\/ISSCC.2014.6757415).","DOI":"10.1109\/ISSCC.2014.6757415"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] L. Chang, <i>et al.<\/i>: \u201cAn 8 T-SRAM for variability tolerance and low-voltage operation in high-performance caches,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 956 (DOI: 10.1109\/JSSC.2007.917509).","DOI":"10.1109\/JSSC.2007.917509"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] N. Shibata, <i>et al.<\/i>: \u201cA high-speed low-power multi-VDD CMOS\/SIMOX SRAM with LV-TTL level input\/output pins-write\/read assist techniques for 1-V operated memory cells,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 1856 (DOI: 10.1109\/JSSC.2010.2051262).","DOI":"10.1109\/JSSC.2010.2051262"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] C.-Y. Tseng, <i>et al.<\/i>: \u201cAn integrated linear regulator with fast output voltage transition for dual-supply SRAMs in DVFS systems,\u201d IEEE J. Solid-State Circuits <b>45<\/b> (2010) 2239 (DOI: 10.1109\/JSSC.2010.2063990).","DOI":"10.1109\/JSSC.2010.2063990"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] B. Nikolic, <i>et al.<\/i>: \u201cTechnology variability from a design perspective,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>58<\/b> (2011) 1996 (DOI: 10.1109\/TCSI.2011.2165389).","DOI":"10.1109\/TCSI.2011.2165389"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] B.S. Amrutur, <i>et al.<\/i>: \u201cA replica technique for wordline and sense control in low-power SRAM\u2019s,\u201d IEEE J. Solid-State Circuits <b>33<\/b> (1998) 1208 (DOI: 10.1109\/4.705359).","DOI":"10.1109\/4.705359"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] C.D.C. Arandilla, <i>et al.<\/i>: \u201cComparison of replica bitline technique and chain delay technique as read timing control for low power asynchronous SRAM,\u201d 2011 Fifth Asia Modelling Symposium (2011) (DOI: 10.1109\/AMS.2011.58).","DOI":"10.1109\/AMS.2011.58"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] S. Komatsu, <i>et al.<\/i>: \u201cA 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation,\u201d Proc. IEEE Custom. Integr. Circuits Conf. (2009) (DOI: 10.1109\/cicc.2009.5280731).","DOI":"10.1109\/CICC.2009.5280731"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Y. Niki, <i>et al.<\/i>: \u201cA digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers,\u201d IEEE J. Solid-State Circuits <b>46<\/b> (2011) 2545 (DOI: 10.1109\/JSSC.2011.2164294).","DOI":"10.1109\/JSSC.2011.2164294"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Z. Lin, <i>et al.<\/i>: \u201cA pipeline replica bitline technique for suppressing timing variation of SRAM sense amplififiers in a 28-nm CMOS process,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 669 (DOI: 10.1109\/JSSC.2016.2634701).","DOI":"10.1109\/JSSC.2016.2634701"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Y. Aoyagi, <i>et al.<\/i>: \u201cA 3-nm FinFET 27.6-\u2006Mbit\/mm<sup>2<\/sup> single-port 6T SRAM enabling 0.48-1.2\u2006V wide operating range with far-end pre-charge and weak-bit tracking,\u201d IEEE J. Solid-State Circuits <b>59<\/b> (2024) 1225 (DOI: 10.1109\/JSSC.2024.3355447).","DOI":"10.1109\/JSSC.2024.3355447"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] X. Qiao, <i>et al.<\/i>: \u201cA 65\u2006nm 73\u2006kb SRAM-based computing-in-memory macro with dynamic-sparsity controlling,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 2977 (DOI: 10.1109\/TCSII.2022.3162017).","DOI":"10.1109\/TCSII.2022.3162017"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Zhou, <i>et al.<\/i>: \u201cMTJ-LRB: proposal of MTJ-based loop replica bitline as MRAM device-circuit interaction for PVT-robust sensing,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 3352 (DOI: 10.1109\/TCSII.2020.2980331).","DOI":"10.1109\/TCSII.2020.2980331"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J. Wu, <i>et al.<\/i>: \u201cA multiple-stage parallel replica-bitline delay addition technique for reducing timing variation of SRAM sense amplifiers,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>61<\/b> (2014) 264 (DOI: 10.1109\/TCSII.2014.2304893).","DOI":"10.1109\/TCSII.2014.2304893"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] T. Kim, <i>et al.<\/i>: \u201cA contention-free wordline supporting circuit for high wordline resistance in sub-10-nm SRAM designs,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2014) 4531 (DOI: 10.1109\/TCSII.2024.3407592).","DOI":"10.1109\/TCSII.2024.3407592"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Yoshisato, <i>et al.<\/i>: \u201cDisturbance aware dynamic power reduction in synchronous 2RW dual-port 8T SRAM by self-adjusting wordline pulse timing,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 2098 (DOI: 10.1109\/JSSC.2022.3229828).","DOI":"10.1109\/JSSC.2022.3229828"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] H. Jeong, <i>et al.<\/i>: \u201cBitline charge-recycling SRAM write assist circuitry for <i>V<\/i><sub>MIN<\/sub> improvement and energy saving,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 896 (DOI: 10.1109\/JSSC.2018.2883725).","DOI":"10.1109\/JSSC.2018.2883725"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] J. Yang, <i>et al.<\/i>: \u201cA double sensing scheme with selective bitline voltage regulation for ultralow-voltage timing speculative SRAM,\u201d IEEE J. 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Wang, <i>et al.<\/i>: \u201cRead bitline sensing and fast local write-back techniques in hierarchical bitline architecture for ultralow-voltage SRAMs,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>24<\/b> (2016) 2165 (DOI: 10.1109\/TVLSI.2015.2499441).","DOI":"10.1109\/TVLSI.2015.2499441"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] A.T. Do, <i>et al.<\/i>: \u201c0.2\u2006V 8T SRAM with PVT-aware bitline sensing and column-based data randomization,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 1487 (DOI: 10.1109\/JSSC.2016.2540799).","DOI":"10.1109\/JSSC.2016.2540799"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T.-H. Kim, <i>et al.<\/i>: \u201cA contention-free wordline supporting circuit for high wordline resistance in sub-10-nm SRAM designs,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 4531 (DOI: 10.1109\/TCSII.2024.3407592).","DOI":"10.1109\/TCSII.2024.3407592"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] J. Kim, <i>et al.<\/i>: \u201cA 4.13-GHz UHS pseudo two-port SRAM with BL charge time reduction and flying word-line for HPC applications in 4-nm FinFET technology,\u201d IEEE J. Solid-State Circuits <b>59<\/b> (2024) 1216 (DOI: 10.1109\/JSSC.2024.3355948).","DOI":"10.1109\/JSSC.2024.3355948"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] C. Peng, <i>et al.<\/i>: \u201cA novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier,\u201d IEICE Electron. Express <b>12<\/b> (2015) 20150102 (DOI: 10.1587\/elex.12.20150102).","DOI":"10.1587\/elex.12.20150102"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] W. Lu, <i>et al.<\/i>: \u201cEfficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers,\u201d Electronics Letters <b>51<\/b> (2015) 742 (DOI: 10.1049\/el.2015.0574).","DOI":"10.1049\/el.2015.0574"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] J. Park, <i>et al.<\/i>: \u201cVoltage boosted fail detecting circuit for selective write assist and cell current boosting for high-density low-power SRAM,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>70<\/b> (2023) 797 (DOI: 10.1109\/TCSI.2022.3226464).","DOI":"10.1109\/TCSI.2022.3226464"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] Y. Li, <i>et al.<\/i>: \u2018An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing,\u2019\u2019 IEICE Electron. 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