{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:24:04Z","timestamp":1772119444381,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,3,25]]},"DOI":"10.1587\/elex.22.20240745","type":"journal-article","created":{"date-parts":[[2025,2,6]],"date-time":"2025-02-06T22:12:36Z","timestamp":1738879956000},"page":"20240745-20240745","source":"Crossref","is-referenced-by-count":3,"title":["A pipelined ADC calibration technique based on time-delay neural network with ant colony optimization"],"prefix":"10.1587","volume":"22","author":[{"given":"Long","family":"Li","sequence":"first","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongsheng","family":"Yin","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhui","family":"Guo","sequence":"additional","affiliation":[{"name":"Institute of Chip Technology, Chery Automotive"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongshun","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Chip Technology, Chery Automotive"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiashen","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Honghui","family":"Deng","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongmei","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luotian","family":"Wu","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muqi","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Hefei University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Hao, <i>et al<\/i>.: \u201c10.2 A single-channel 2.6\u2006GS\/s 10b dynamic pipelined ADC with time-assisted residue generation scheme achieving intrinsic PVT robustness,\u201d ISSCC Dig. Tech. Papers (2023) 168 (DOI: 10.1109\/ISSCC42615.2023.10067822).","DOI":"10.1109\/ISSCC42615.2023.10067822"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Q. Liu, <i>et al<\/i>.: \u201cA 1-GS\/s 11-bit SAR-assisted pipeline ADC with 59-dB SNDR in 65-Nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1164 (DOI: 10.1109\/\/TCSII.2018.2814581).","DOI":"10.1109\/TCSII.2018.2814581"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] H. Liu, <i>et al<\/i>.: \u201cA 1\u2006GS\/s 12-bit pipelined folding ADC with a novel encoding algorithm,\u201d IEICE Electron. Express <b>16<\/b> (2019) 20181150 (DOI: 10.1587\/elex.16.20181150).","DOI":"10.1587\/elex.16.20181150"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] C. Zhu, <i>et al<\/i>.: \u201cAnalysis and design of a large dither injection circuit for improving linearity in pipelined ADCs,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>27<\/b> (2019) 2008 (DOI: 10.1109\/TVLSI.2019.2912421).","DOI":"10.1109\/TVLSI.2019.2912421"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Z. Xiong, <i>et al<\/i>.: \u201cDigital background calibration for a 14-bit 100-MS\/s pipelined ADC using signal-dependent dithering,\u201d IEICE Trans. Electron. <b>E97-C<\/b> (2014) 207 (DOI: 10.1587\/transele.E97.C.207).","DOI":"10.1587\/transele.E97.C.207"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14\u2006bit 1\u2006GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/JSSC.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] J. Lagos, <i>et al<\/i>.: \u201cA 10.1-ENOB, 6.2-fJ\/conv.-step, 500-MS\/s, ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 1112 (DOI: 10.1109\/JSSC.2021.3133829).","DOI":"10.1109\/JSSC.2021.3133829"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L. Wei, <i>et al<\/i>.: \u201cA 12-bit 1\u2006GS\/s ADC with background distortion and split-ADC-like gain calibration,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>70<\/b> (2023) 4679 (DOI: 10.1109\/TCSI.2023.3303217).","DOI":"10.1109\/TCSI.2023.3303217"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] X. Hou, <i>et al<\/i>.: \u201cA 12-bit 50\u2006MS\/s SAR ADC with non-binary split capacitive DAC in 40\u2006nm CMOS,\u201d IEICE Electron. Express <b>21<\/b> (2024) 20240311 (DOI: 10.1587\/elex.21.20240311).","DOI":"10.1587\/elex.21.20240311"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Y. Zhou, <i>et al<\/i>.: \u201cA 12-b 1-GS\/s 31.5-mW time-interleaved SAR ADC with analog HPF-assisted skew calibration and randomly sampling reference ADC,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 2207 (DOI: 10.1109\/JSSC.2019.2915583).","DOI":"10.1109\/JSSC.2019.2915583"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] F. Solis, <i>et al<\/i>.: \u201cError-backpropagation-based background calibration of TI-ADC for adaptively equalized digital communication receivers,\u201d IEEE Access <b>10<\/b> (2022) 103013 (DOI: 10.1109\/ACCESS.2022.3208092).","DOI":"10.1109\/ACCESS.2022.3208092"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] H. Deng, <i>et al<\/i>.: \u201cAn efficient background calibration technique for analog-to-digital converters based on neural network,\u201d Integration <b>74<\/b> (2020) 63 (DOI: 10.1016\/j.vlsi.2020.04.003).","DOI":"10.1016\/j.vlsi.2020.04.003"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] L. Li, <i>et al<\/i>.: \u201cGenetic neural network based background calibration method for pipeline ADC,\u201d Microelectronics Journal <b>151<\/b> (2024) 106317 (DOI: 10.1016\/j.mejo.2024.106317).","DOI":"10.1016\/j.mejo.2024.106317"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] D. Zhai, <i>et al<\/i>.: \u201cHigh-speed and time-interleaved ADCs using additive-neural-network-based calibration for nonlinear amplitude and phase distortion,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 4944 (DOI: 10.1109\/TCSI.2022.3201016).","DOI":"10.1109\/TCSI.2022.3201016"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] H. Lu, <i>et al<\/i>.: \u201cA digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm,\u201d Microelectronics Journal. <b>114<\/b> (2021) 105113 (DOI: 10.1016\/j.mejo.2021.105113).","DOI":"10.1016\/j.mejo.2021.105113"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] H. Liu, <i>et al<\/i>.: \u201cA convolutional neural network based calibration scheme for pipelined ADC,\u201d ISCAS (2023) 1 (DOI: 10.1109\/ISCAS46773.2023.10181892).","DOI":"10.1109\/ISCAS46773.2023.10181892"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] J. Zeng, <i>et al<\/i>.: \u201cAn analog-to-digital converter calibration algorithm with clock jitter compensation based on bidirectional long-short-time-memory,\u201d Electron. Lett. <b>58<\/b> (2022) 753 (DOI: 10.1049\/ell2.12598).","DOI":"10.1049\/ell2.12598"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] T. Zhang, <i>et al<\/i>.: \u201cMachine learning based prior-knowledge-free calibration for split pipelined-SAR ADCs with open-loop amplifiers achieving 93.7-dB SFDR,\u201d ESSCIRC (2019) 189 (DOI: 10.1109\/ESSCIRC.2019.8902873).","DOI":"10.1109\/ESSCIRC.2019.8902873"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] Y. Xiang, <i>et al<\/i>.: \u201cA neural network based background calibration for pipelined-SAR ADCs at low hardware cost,\u201d Electronics Letters <b>59<\/b> (2023) e12909 (DOI: 10.1049\/ell2.12909).","DOI":"10.1049\/ell2.12909"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] S. Bansal, <i>et al<\/i>.: \u201cNeural-network based self-initializing algorithm for multi-parameter optimization of high-speed ADCs,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 106 (DOI: 10.1109\/TCSII.2020.3012386).","DOI":"10.1109\/TCSII.2020.3012386"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] H. Deng, <i>et al<\/i>.: \u201cMachine-learning based nonlinerity correction for coarse-fine SAR-TDC hybrid ADC,\u201d MWSCAS (2020) 265 (DOI: 10.1109\/MWSCAS48704.2020.9184523).","DOI":"10.1109\/MWSCAS48704.2020.9184523"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] X. Peng, <i>et al<\/i>.: \u201cA neural network based calibration technique for TI-ADCs with derivative information,\u201d ISCAS (2023) 1 (DOI: 10.1109\/ISCAS46773.2023.10181825).","DOI":"10.1109\/ISCAS46773.2023.10181825"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] Y. Qiu, <i>et al<\/i>.: \u201cA novel calibration method of gain and time-skew mismatches for time-interleaved ADCs based on neural network,\u201d IWS (2019) 1 (DOI: 10.1109\/IEEE-IWS.2019.8804030).","DOI":"10.1109\/IEEE-IWS.2019.8804030"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] Z. Lu, <i>et al<\/i>.: \u201cA new artificial neural network-based calibration mechanism for ADCs: a time-interleaved ADC case study,\u201d IEEE Trans. Very Lagre Scale Integr. (VLSI) Syst. <b>32<\/b> (2024) 1184 (DOI: 10.1109\/TVLSI.2024.3390220).","DOI":"10.1109\/TVLSI.2024.3390220"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] S.-W.M. Chen, <i>et al<\/i>.: \u201cA 6-bit 600-MS\/s 5.3-mW asynchronous ADC in 0.13-<i>\u03bc<\/i>m CMOS,\u201d IEEE J. Solid-State Circuits <b>41<\/b> (2006) 2669 (DOI: 10.1109\/JSSC.2006.884231).","DOI":"10.1109\/JSSC.2006.884231"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] B. Xue, <i>et al<\/i>.: \u201cA sinusoidal fitting-based digital foreground calibration technique for pipelined ADC,\u201d ASICON (2023) 1 (DOI: 10.1109\/ASICON58565.2023.10396150).","DOI":"10.1109\/ASICON58565.2023.10396150"},{"key":"27","unstructured":"[27] A. Colorni, <i>et al<\/i>.: \u201cDEACO: distributed optimization by ant colonies,\u201d Proc. 1st Eur. Conf. Artif. Life (1991) 134."},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] S. Ebadinezhad, <i>et al<\/i>.: \u201cAdopting dynamic evaporation strategy to enhance ACO algorithm for the traveling salesman problem,\u201d Engineering Applications of Artificial Intelligence <b>92<\/b> (2020) 103649 (DOI: 10.1016\/j.engappai.2020.103649).","DOI":"10.1016\/j.engappai.2020.103649"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] C. Miao, <i>et al<\/i>.: \u201cPath planning optimization of indoor mobile robot based on adaptive ant colony algorithm,\u201d Computers &amp; Industrial Engineering <b>156<\/b> (2021) 107230 (DOI: 10.1016\/j.cie.2021.107230).","DOI":"10.1016\/j.cie.2021.107230"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] M. Mavrovouniotis and S. Yang: \u201cTraining neural networks with ant colony optimization algorithms for pattern classification,\u201d Soft Computing <b>19<\/b> (2015) 1511 (DOI: 10.1007\/s00500-014-1334-5).","DOI":"10.1007\/s00500-014-1334-5"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/6\/22_22.20240745\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,29]],"date-time":"2025-03-29T04:10:50Z","timestamp":1743221450000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/6\/22_22.20240745\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,25]]},"references-count":30,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20240745","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3,25]]},"article-number":"22.20240745"}}