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Im, <i>et al<\/i>.: \u201cA 112-Gb\/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR ADC and inverter-based RX analog front-end in 7-nm FinFET,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 7 (DOI: 10.1109\/JSSC.2020.3024261).","DOI":"10.1109\/JSSC.2020.3024261"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Y. Zhang and Q. Hu: \u201cA 33\u2006Gb\/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13\u2006<i>\u03bc<\/i>m BiCMOS technology for serial link,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20170764 (DOI: 10.1587\/elex.15.20170764).","DOI":"10.1587\/elex.15.20170764"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] H. Sun, <i>et al<\/i>.: \u201c6.25-10\u2006Gb\/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18\u2006<i>\u03bc<\/i>m CMOS,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220429 (DOI: 10.1587\/elex.19.20220429).","DOI":"10.1587\/elex.19.20220429"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A. Roshan-Zamir, <i>et al<\/i>.: \u201cA 56-Gb\/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 672 (DOI: 10.1109\/JSSC.2018.2881278).","DOI":"10.1109\/JSSC.2018.2881278"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] G. Kim, <i>et al<\/i>.: \u201cA 161-mW 56-Gb\/s ADC-based discrete multitone wireline receiver data-path in 14-nm FinFET,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 38 (DOI: 10.1109\/JSSC.2019.2938414).","DOI":"10.1109\/JSSC.2019.2938414"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y. Frans, <i>et al.<\/i>: \u201cA 56-Gb\/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET,\u201d IEEE J. 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Razavi: \u201cA 56-Gb\/s 50-mW NRZ receiver in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 54 (DOI: 10.1109\/JSSC.2021.3109032).","DOI":"10.1109\/JSSC.2021.3109032"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Khairi, <i>et al.<\/i>: \u201cA 1.41-pJ\/b 224-Gb\/s PAM4 6-bit ADC-based SerDes receiver with hybrid AFE capable of supporting long reach channels,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 8 (DOI: 10.1109\/jssc.2022.3211475).","DOI":"10.1109\/JSSC.2022.3211475"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] S. Kiran, <i>et al.<\/i>: \u201cA 56\u2006GHz receiver analog front end for 224\u2006Gb\/s PAM-4 SerDes in 10\u2006nm CMOS,\u201d 2021 Symp. VLSI Circuits (2021) 1 (DOI: 10.23919\/VLSICIRCUITS52068.2021.9492471).","DOI":"10.23919\/VLSICircuits52068.2021.9492471"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] Y. Krupnik, <i>et al.<\/i>: \u201c112\u2006Gb\/s PAM4 ADC based SERDES receiver for long-reach channels in 10\u2006nm process,\u201d 2019 Symp. VLSI CircuitsC (2019) C266 (DOI: 10.23919\/vlsic.2019.8778136).","DOI":"10.23919\/VLSIC.2019.8778136"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] R. Tang, <i>et al.<\/i>: \u201cA continuous-time linear equalizer with ultrafine gain adjustment achieving 0.3-dB DC-gain step and 0.9-dB peaking-gain step,\u201d IEEE Microw. Wireless Technol. Lett. <b>33<\/b> (2023) 559 (DOI: 10.1109\/LMWT.2022.3233634).","DOI":"10.1109\/LMWT.2022.3233634"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] D. Wang, <i>et al<\/i>.: \u201cA 56-Gbps PAM-4 wireline receiver with 4-tap direct DFE employing dynamic CML comparators in 65\u2006nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 1027 (DOI: 10.1109\/TCSI.2021.3125355).","DOI":"10.1109\/TCSI.2021.3125355"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] I. Petricli, <i>et al<\/i>.: \u201cA 112\u2006Gb\/s PAM-4 RX front-end with unclocked decision feedback equalizer,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 256 (DOI: 10.1109\/TCSII.2020.3011972).","DOI":"10.1109\/TCSII.2020.3011972"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] K.-C. Chen, <i>et al<\/i>.: \u201cA 60-Gb\/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 750 (DOI: 10.1109\/jssc.2020.3025285).","DOI":"10.1109\/JSSC.2020.3025285"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] J. Sim, <i>et al<\/i>.: \u201cA 25\u2006Gb\/s wireline receiver with feedforward and feedback equalizers at analog front-end,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 404 (DOI: 10.1109\/TCSII.2021.3093913).","DOI":"10.1109\/TCSII.2021.3093913"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Y. Lv, <i>et al<\/i>.: \u201cA 50\u2006Gb\/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation,\u201d IEICE Electron. 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