{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,10]],"date-time":"2025-05-10T04:10:02Z","timestamp":1746850202365,"version":"3.40.5"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"9","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,5,10]]},"DOI":"10.1587\/elex.22.20250091","type":"journal-article","created":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T22:06:04Z","timestamp":1742940364000},"page":"20250091-20250091","source":"Crossref","is-referenced-by-count":0,"title":["A 0.014%\/V LS and -73.5\u2006dB PSRR 5-T voltage reference with enhanced self regulation"],"prefix":"10.1587","volume":"22","author":[{"given":"Kai","family":"Yu","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhong","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Information Engineering, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sizhen","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Y. Meng, <i>et al<\/i>.: \u201cA -80\u2006dB PSRR 1.166\u2006ppm\/\u00b0C bandgap voltage reference with improved high-order temperature compensation,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230278 (DOI: 10.1587\/elex.20.20230278).","DOI":"10.1587\/elex.20.20230278"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H.M. Chen, <i>et al<\/i>.: \u201cA sub-1\u2006ppm\/\u00b0C precision bandgap reference with adjusted-temperature-curvature compensation,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>64<\/b> (2017) 1308 (DOI: 10.1109\/TCSI.2017.2658186).","DOI":"10.1109\/TCSI.2017.2658186"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] G. Pan, <i>et al<\/i>.: \u201cA 1.8\u2006V 0.918\u2006ppm\/\u00b0C CMOS bandgap voltage reference with curvature-compensated,\u201d IEICE Electron. Express <b>16<\/b> (2019) 20190616 (DOI: 10.1587\/elex.16.20190616).","DOI":"10.1587\/elex.16.20190616"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] X. Liu, <i>et al<\/i>.: \u201cA 2.5\u2006ppm\/\u00b0C voltage reference combining traditional BGR and ZTC MOSFET high-order curvature compensation,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 1093 (DOI: 10.1109\/TCSII.2020.3027768).","DOI":"10.1109\/TCSII.2020.3027768"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] W. Yu, <i>et al<\/i>.: \u201cA 2.2\u2006ppm\/\u00b0C compensated bandgap voltage reference with a double-ended current trimming technique,\u201d IEICE Electron. Express <b>19<\/b> (2022) 20220390 (DOI: 10.1587\/elex.19.20220390).","DOI":"10.1587\/elex.19.20220390"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] K. Chen, <i>et al<\/i>.: \u201cA 1.16-V 5.8-to-13.5-ppm\/\u00b0C curvature-compensated CMOS bandgap reference circuit with a shared offset-cancellation method for internal amplifiers,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 267 (DOI: 10.1109\/JSSC.2020.3033467).","DOI":"10.1109\/JSSC.2020.3033467"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] N. Liu, <i>et al<\/i>.: \u201cSub-ppm\/\u00b0C bandgap references with natural basis expansion for curvature cancellation,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 3551 (DOI: 10.1109\/TCSI.2021.3096166).","DOI":"10.1109\/TCSI.2021.3096166"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] C.F. Lee, <i>et al<\/i>.: \u201cA 0.5\u2006V 22.5\u2006ppm\/\u00b0C bandgap voltage reference with leakage current injection for curvature correction,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>70<\/b> (2023) 3897 (DOI: 10.1109\/TCSII.2023.3295187).","DOI":"10.1109\/TCSII.2023.3295187"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Y. Liu, <i>et al<\/i>.: \u201cA 0.4-V wide temperature range all-MOSFET subthreshold voltage reference with 0.027%\/V line sensitivity,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 969 (DOI: 10.1109\/TCSII.2018.2794512).","DOI":"10.1109\/TCSII.2018.2794512"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] L. Wang and C. Zhan: \u201cA 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 3457 (DOI: 10.1109\/TCSI.2019.2927240).","DOI":"10.1109\/TCSI.2019.2927240"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] C. Huang, <i>et al<\/i>.: \u201cA 0.6-V minimum-supply, 23.5\u2006ppm\/\u00b0C subthreshold CMOS voltage reference with 0.45% variation coefficient,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 1290 (DOI: 10.1109\/TCSII.2018.2846808).","DOI":"10.1109\/TCSII.2018.2846808"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. Pullela, <i>et al<\/i>.: \u201cA 156\u2006pW gate-leakage based voltage\/current reference for low-power IoT systems,\u201d Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) (2022) (DOI: 10.1109\/ISCAS48785.2022.9937316).","DOI":"10.1109\/ISCAS48785.2022.9937316"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] K. Yu, <i>et al<\/i>.: \u201cA 521\u2006pW, 0.016%\/V line sensitivity self-biased CMOS voltage reference with DIBL effect compensation using adaptive VGS control,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 1754 (DOI: 10.1109\/TCSII.2023.3328867).","DOI":"10.1109\/TCSII.2023.3328867"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Wang, <i>et al<\/i>.: \u201cA 48\u2006pW, 0.34\u2006V, 0.019%\/V line sensitivity selfbiased subthreshold voltage reference with DIBL effect compensation,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 611 (DOI: 10.1109\/TCSI.2019.2946680).","DOI":"10.1109\/TCSI.2019.2946680"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K. Yu, <i>et al<\/i>.: \u201cA 353\u2006pW, 0.014%\/V line sensitivity self-biased CMOS voltage reference with source degeneration active load,\u201d IEICE Electron. Express <b>21<\/b> (2024) 20230497 (DOI: 10.1587\/elex.20.20230497).","DOI":"10.1587\/elex.20.20230497"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] K. Yu, <i>et al<\/i>.: \u201cA 0.011%\/V LS and -76-dB PSRR self-biased CMOS voltage reference with quasi self-cascode current mirror,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 1052 (DOI: 10.1109\/TCSII.2023.3318372).","DOI":"10.1109\/TCSII.2023.3318372"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] C. Shao, <i>et al<\/i>.: \u201cA 1.8-nW, -73.5-dB PSRR, 0.2-ms startup CMOS voltage reference,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2020) 1795 (DOI: 10.1109\/JSSC.2020.3028506).","DOI":"10.1109\/JSSC.2020.3028506"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J. Duan, <i>et al<\/i>.: \u201cA novel 0.8-V 79-nW CMOS-only voltage reference with -55-dB PSRR @ 100\u2006Hz,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>65<\/b> (2018) 849 (DOI: 10.1109\/TCSII.2017.2728700).","DOI":"10.1109\/TCSII.2017.2728700"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] Y. Chen and J. Guo: \u201cA 42\u2006nA <i>I<sub>Q<\/sub><\/i>, 1.5-6\u2006V <i>V<sub>IN<\/sub><\/i>, self-regulated CMOS voltage reference with -93\u2006dB PSR at 10\u2006Hz for energy harvesting systems,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 6357 (DOI: 10.1109\/TCSII.2021.3058716).","DOI":"10.1109\/TCSII.2021.3058716"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] H. Qiao, <i>et al<\/i>.: \u201cA -40\u00b0C to 140\u00b0C picowatt CMOS voltage reference with 0.25-V power supply,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>68<\/b> (2021) 3118 (DOI: 10.1109\/TCSII.2021.3088157).","DOI":"10.1109\/TCSII.2021.3088157"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] H. Xu, <i>et al<\/i>.: \u201c98\u2006pA, 0.17\u2006ppmV, -72\u2006dB@100\u2006Hz voltage reference for Internet-of-Things systems,\u201d IEICE Electron. Express <b>15<\/b> (2018) 20180965 (DOI: 10.1587\/elex.15.20180965).","DOI":"10.1587\/elex.15.20180965"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] X. Yang, <i>et al<\/i>.: \u201cAn AC-coupled 1st-order \u0394-\u0394\u03a3 readout IC for area-efficient neural signal acquisition,\u201d IEEE J. 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Briefs <b>68<\/b> (2021) 587 (DOI: 10.1109\/TCSII.2020.3046368).","DOI":"10.1109\/TCSII.2020.3046368"},{"key":"29","unstructured":"[29] B. Razavi: <i>Design of Analog CMOS Integrated Circuits<\/i> (McGrawHill, USA, 2001) 23."},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] J. Hu, <i>et al<\/i>.: \u201cA 1.8-nW sub-1-V self-biased sub-bandgap reference for low-power systems,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210204 (DOI: 10.1587\/elex.18.20210204).","DOI":"10.1587\/elex.18.20210204"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] M. Lefebvre and D. Bol: \u201cA family of current references based on 2T voltage references: demonstration in 0.18-<i>\u03bc<\/i>m with 0.1-nA PTAT and 1.1-<i>\u03bc<\/i>A CWT 38-ppm\/\u00b0C designs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 3237 (DOI: 10.1109\/TCSI.2022.3172647).","DOI":"10.1109\/TCSI.2022.3172647"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/9\/22_22.20250091\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,10]],"date-time":"2025-05-10T03:54:11Z","timestamp":1746849251000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/9\/22_22.20250091\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,10]]},"references-count":31,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250091","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,5,10]]},"article-number":"22.20250091"}}