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Solid-State Circuits <b>52<\/b> (2017) 3204 (DOI: 10.1109\/JSSC.2017.2747758).","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14-bit 2.5\u2006GS\/s and 5\u2006GS\/s RF sampling ADC with background calibration and dither,\u201d VLSI (2016) 1 (DOI: 10.1109\/VLSIC.2016.7573537).","DOI":"10.1109\/VLSIC.2016.7573537"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14\u2006bit 1\u2006GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/JSSC.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] L. Wei, <i>et al<\/i>.: \u201cA 12-bit 1\u2006GS\/s ADC with background distortion and split-ADC-like gain calibration,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>70<\/b> (2023) 4679 (DOI: 10.1109\/TCSI.2023.3303217).","DOI":"10.1109\/TCSI.2023.3303217"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] X. Guo, <i>et al<\/i>.: \u201cA 12-bit 2.3\u20062GS\/s pipelined\/SAR hybrid ADC with a high-linearity input buffer,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230369 (DOI: 10.1587\/elex.20.20230369).","DOI":"10.1587\/elex.20.20230369"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] F. Xu, <i>et al<\/i>.: \u201cA 12-bit 1-GS\/s pipelined ADC with a novel timing strategy in 40-nm CMOS process,\u201d MDPI Electron. <b>12<\/b> (2023) 924 (DOI: 10.3390\/electronics12040924).","DOI":"10.3390\/electronics12040924"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] C. Zhang, <i>et al<\/i>.: \u201cA 12-bit 1.25\u2006GS\/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique,\u201d Microelectron. J. <b>130<\/b> (2022) 105611 (DOI: 10.1016\/j.mejo.2022.105611).","DOI":"10.1016\/j.mejo.2022.105611"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] D. Li, <i>et al<\/i>.: \u201cA wideband input buffer based on cascade complementary source follower,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>32<\/b> (2024) 962 (DOI: 10.1109\/TVLSI.2024.3349564).","DOI":"10.1109\/TVLSI.2024.3349564"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] J. Nan, <i>et al<\/i>.: \u201cAn 8-GHz bandwidth push-pull input buffer based on cascode source follower,\u201d ICCS (2023) 70 (DOI: 10.1109\/ICCS59502.2023.10367338).","DOI":"10.1109\/ICCS59502.2023.10367338"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Huang, <i>et al<\/i>.: \u201cA 6-GHz bandwidth input buffer based on AC-coupled flipped source follower for 12-bit 8-GS\/s ADC in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 4163 (DOI: 10.1109\/TCSII.2022.3188534).","DOI":"10.1109\/TCSII.2022.3188534"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] T. Li, <i>et al<\/i>.: \u201cWide-band input buffer with optimized linearity for high-speed high-resolution ADCs,\u201d ASID (2020) 116 (DOI: 10.1109\/ASID50160.2020.9271786)","DOI":"10.1109\/ASID50160.2020.9271786"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Z. Huang, <i>et al<\/i>.: \u201cLow-voltage high-linearity differential input buffer with current amplifier feed-forward compensation for high-speed ADCs,\u201d ICTA (2020) 41 (DOI: 10.1109\/ICTA50426.2020.9332138).","DOI":"10.1109\/ICTA50426.2020.9332138"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Z. Wu, <i>et al<\/i>.: \u201cAn ADC input buffer with optimized linearity,\u201d 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2018) 1 (DOI: 10.1109\/ICSICT.2018.8564827).","DOI":"10.1109\/ICSICT.2018.8564827"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Y. Kong, <i>et al<\/i>.: \u201cAn ultra low output resistance and wide swing voltage follower,\u201d 2007 International Conference on Communications, Circuits and Systems (2007) 1007 (DOI: 10.1109\/ICCCAS.2007.4348217).","DOI":"10.1109\/ICCCAS.2007.4348217"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Koutani, <i>et al<\/i>.: \u201cA highly linear CMOS buffer circuit with an adjustable output impedance,\u201d Proc. IEEE 2003 Custom Integrated Circuits Conference (2003) 685 (DOI: 10.1109\/CICC.2003.1249486).","DOI":"10.1109\/CICC.2003.1249486"},{"key":"18","unstructured":"[18] K. Wada and Y. Tadokoro: \u201cDesign of a body-effect reduced-source follower and its application to linearization technique,\u201d Proc. 2002 IEEE International Symposium on Circuits and Systems (Cat. no.02CH37353) (2002) III (DOI: 10.1109\/ISCAS.2002.1010326)."},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] X. Fan and P.K. Chan: \u201cAnalysis and design of low-distortion CMOS source followers,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>52<\/b> (2005) 1489 (DOI: 10.1109\/TCSI.2005.851711).","DOI":"10.1109\/TCSI.2005.851711"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Y. Cheng, <i>et al<\/i>.: \u201cHigh linearity front-end circuit for RF sampling ADCs with nonlinear junction capacitor cancellation,\u201d 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (2023) 1 (DOI: 10.1109\/ISCAS46773.2023.10181839).","DOI":"10.1109\/ISCAS46773.2023.10181839"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C. Huang, <i>et al<\/i>.: \u201cAn input buffer with 85\u2006dB SFDR for high-speed pipeline ADC,\u201d ICTA (2022) 52 (DOI: 10.1109\/ICTA56932.2022.9962993).","DOI":"10.1109\/ICTA56932.2022.9962993"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] L. Scaletti, <i>et al<\/i>.: \u201cA novel push-pull input buffer for wideband ADCs with improved high-frequency linearity,\u201d NEWCAS (2023) 1 (DOI: 10.1109\/NEWCAS57931.2023.10198057).","DOI":"10.1109\/NEWCAS57931.2023.10198057"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] T. Feng, <i>et al<\/i>.: \u201cA wideband high-linearity input buffer based on cascade complementary source follower,\u201d ICTA (2022) 13 (DOI: 10.1109\/ICTA56932.2022.9962966).","DOI":"10.1109\/ICTA56932.2022.9962966"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] L. Zhang, <i>et al<\/i>.: \u201cAn input buffer for 4\u2006GS\/s 14-b time-interleaved ADC,\u201d ASICON (2021) 1 (DOI: 10.1109\/ASICON52560.2021.9620387).","DOI":"10.1109\/ASICON52560.2021.9620387"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] T. Feng, <i>et al<\/i>.: \u201cA wideband ADC input buffer based on AC-coupled super source follower,\u201d 2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT) (2023) 1 (DOI: 10.1109\/ICMMT58241.2023.10277138).","DOI":"10.1109\/ICMMT58241.2023.10277138"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] Z. Liu, <i>et al<\/i>.: \u201cA 0.5-V 3.69-nW complementary source-follower-C based low-pass filter for wearable biomedical applications,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>67<\/b> (2020) 4370 (DOI: 10.1109\/TCSI.2020.2995351).","DOI":"10.1109\/TCSI.2020.2995351"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] Y. Chen, <i>et al<\/i>.: \u201cA wide-band input buffer for 3\u2006GS\/s 12\u2006bit time-interleaved ADC,\u201d ICSICT (2016) 1467 (DOI: 10.1109\/ICSICT.2016.7998771).","DOI":"10.1109\/ICSICT.2016.7998771"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] R.G. Carvajal, <i>et al<\/i>.: \u201cThe flipped voltage follower: a useful cell for low-voltage low-power circuit design,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>52<\/b> (2005) 1276 (DOI: 10.1109\/TCSI.2005.851387).","DOI":"10.1109\/TCSI.2005.851387"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] Y. Cao, <i>et al<\/i>.: \u201cAn operational amplifier assisted input buffer and an improved bootstrapped switch for high-speed and high-resolution ADCs,\u201d 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (2018) 1 (DOI: 10.1109\/ISCAS.2018.8351071).","DOI":"10.1109\/ISCAS.2018.8351071"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] S. Chakraborty, <i>et al<\/i>.: \u201cLinearity improvement of gain enhanced op-amp using cross-coupled architecture,\u201d Microsyst. Technol. <b>24<\/b> (2018) 4807 (DOI: 10.1007\/s00542-018-3885-3).","DOI":"10.1007\/s00542-018-3885-3"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] F. Cao, <i>et al<\/i>.: \u201cAn input buffer for 12\u2006bit 2\u2006GS\/s ADC,\u201d ASICON (2017) 750 (DOI: 10.1109\/ASICON.2017.8252584).","DOI":"10.1109\/ASICON.2017.8252584"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] H.J. 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