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Liu, <i>et al<\/i>.: \u201c100\u2006Gbps PAM4 VCSEL-based transmission over meter-scale flexible multimode polymer waveguides for board-level optical interconnects application,\u201d Optical Fiber Communications Conference and Exhibition (2024) 1 (DOI: 10.1364\/ofc.2024.w2a.6).","DOI":"10.1364\/OFC.2024.W2A.6"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Z. Zhou, <i>et al<\/i>.: \u201cClock synchronized transmission of 51.2\u2006GBd optical packets for optically switched data center interconnects,\u201d Optical Fiber Communications Conference and Exhibition (2021) 1 (DOI: 10.1364\/ofc.2021.th4e.2).","DOI":"10.1364\/OFC.2021.Th4E.2"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M.G. Ahmed, <i>et al<\/i>.: \u201cA 16-Gb\/s -11.6-dBm OMA sensitivity 0.7-pJ\/bit optical receiver in 65-nm CMOS enabled by duobinary sampling,\u201d IEEE J. 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Park, <i>et al<\/i>.: \u201cA 4.63\u2006pJ\/b 112\u2006Gb\/s DSP-based PAM-4 transceiver for a large-scale switch in 5\u2006nm FinFET,\u201d IEEE International Solid-State Circuits Conference (2023) 5 (DOI: 10.1109\/ISSCC42615.2023.10067613).","DOI":"10.1109\/OJSSCS.2024.3488654"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Y.-P. Lin, <i>et al<\/i>.: \u201c7.7 A 2.16\u2006pJ\/b 112\u2006Gb\/s PAM-4 transceiver with time-interleaved 2b\/3b ADCs and unbalanced baud-rate CDR for XSR applications in 28\u2006nm CMOS,\u201d IEEE International Solid-State Circuits Conference (2024) 136 (DOI: 10.1109\/ISSCC49657.2024.10454418).","DOI":"10.1109\/ISSCC49657.2024.10454418"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. 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Yuminaka: \u201cEfficient PAM-4 data transmission with closed eye using symbol distribution estimation,\u201d IEEE 51st International Symposium on Multiple-Valued Logic (2021) 195 (DOI: 10.1109\/ISMVL51352.2021.00041).","DOI":"10.1109\/ISMVL51352.2021.00041"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] J. Sim, <i>et al<\/i>.: \u201cA wireline transceiver with 3-bit per symbol using common-mode NRZ and differential-mode PAM-4 signaling techniques,\u201d IEEE J. Solid-State Circuits <b>59<\/b> (2024) 2518 (DOI: 10.1109\/JSSC.2024.3358337).","DOI":"10.1109\/JSSC.2024.3358337"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Y. Choi, <i>et al<\/i>.: \u201cA 25-Gb\/s single-ended PAM-4 receiver with time-windowed LSB decoder for high-speed memory interfaces,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 2005 (DOI: 10.1109\/JSSC.2022.3231654).","DOI":"10.1109\/JSSC.2022.3231654"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Z. Zhang, <i>et al<\/i>.: \u201cA 32-Gb\/s 0.46-pJ\/bit PAM4 CDR using a quarter-rate linear phase detector and a self-biased PLL-based multiphase clock generator,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2734 (DOI: 10.1109\/JSSC.2020.3005780).","DOI":"10.1109\/JSSC.2020.3005780"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] M.-A. LaCroix, <i>et al<\/i>.: \u201c8.4 A 116\u2006Gb\/s DSP-based wireline transceiver in 7\u2006nm CMOS achieving 6\u2006pJ\/b at 45\u2006dB loss in PAM-4\/duo-PAM-4 and 52\u2006dB in PAM-2,\u201d IEEE International Solid-State Circuits Conference (2021) 132 (DOI: 10.1109\/ISSCC42613.2021.9366030).","DOI":"10.1109\/ISSCC42613.2021.9366030"},{"key":"19","unstructured":"[19] P. Mishra, <i>et al<\/i>.: \u201c8.7 A 112\u2006Gb\/s ADC-DSP-based PAM-4 transceiver for long-reach applications with &gt; 40\u2006dB channel loss in 7\u2006nm FinFET,\u201d IEEE International Solid-State Circuits Conference (2021) 138 (DOI: 10.1109\/ISSCC42613.2021.9365929)."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Fan, <i>et al<\/i>.: \u201cA 40-Gb\/s PAM-4 transmitter using a 0.16-pJ\/bit SST-CML-hybrid (SCH) output driver and a hybrid-path 3-tap FFE scheme in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>66<\/b> (2019) 4850 (DOI: 10.1109\/TCSI.2019.2936226).","DOI":"10.1109\/TCSI.2019.2936226"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Kim, <i>et al<\/i>.: \u201cA low-power 28-Gb\/s PAM-4MZM driver with level pre-distortion,\u201d IEEE Trans. Circuits Syst. II, Exp. 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Song, <i>et al<\/i>.: \u201cA 35-Gb\/s PAM-4 transmitter with 7B4Q full-transition avoidance and area-efficient Gm-boosting techniques,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 46 (DOI: 10.1109\/TCSII.2023.3302023).","DOI":"10.1109\/TCSII.2023.3302023"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] P.-J. 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