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Ding, <i>et al<\/i>.: \u201cA low-spur MASH delta-sigma modulator with an adaptive length extension technique,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>67<\/b> (2020) 2818 (DOI: 10.1109\/TCSII.2020.2987953).","DOI":"10.1109\/TCSII.2020.2987953"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Y. Fu, <i>et al<\/i>.: \u201cA 32-GHz nested-PLL-based FMCW modulator with 2.16-GHz bandwidth in a 65-nm CMOS process,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>28<\/b> (2020) 1600 (DOI: 10.1109\/TVLSI.2020.2992123).","DOI":"10.1109\/TVLSI.2020.2992123"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M.P. Kennedy, <i>et al<\/i>.: \u201cA method to quantify the dependence of spur heights on offset current in a CP-PLL,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2016) 1658 (DOI: 10.1109\/ISCAS.2016.7538885).","DOI":"10.1109\/ISCAS.2016.7538885"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] D. Mai, <i>et al<\/i>.: \u201cMASH DDSM-induced spurs in a fractional-N frequency synthesizer,\u201d 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2019) 13 (DOI: 10.1109\/ICECS46596.2019.8965008).","DOI":"10.1109\/ICECS46596.2019.8965008"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Pamarti, <i>et al<\/i>.: \u201cStatistics of the quantization noise in 1-bit dithered single-quantizer digital delta\u2006\u2014\u2006sigma modulators,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>54<\/b> (2007) 492 (DOI: 10.1109\/TCSI.2006.887616).","DOI":"10.1109\/TCSI.2006.887616"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] K. Hosseini, <i>et al<\/i>.: \u201cPrediction of the spectrum of a digital delta-sigma modulator followed by a polynomial nonlinearity,\u201d IEEE Trans. Circuits Syst. I, Reg. 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Kennedy: \u201cNonlinearity-induced spurs in fractional-N frequency synthesizers: state of the art,\u201d 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2019) 823 (DOI: 10.1109\/ICECS46596.2019.8965088).","DOI":"10.1109\/ICECS46596.2019.8965088"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Goyal and M.P. Kennedy: \u201cSpur performance and relative implementation costs of MASH and ENOP digital \u0394\u03a3 modulators,\u201d 35th Irish Signals and Systems Conference (ISSC) (2024) 1 (DOI: 10.1109\/ISSC61953.2024.10603135).","DOI":"10.1109\/ISSC61953.2024.10603135"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] X. Lu and M.P. Kennedy: \u201cComparison of the simulated performance of divider controllers for fractional-N frequency synthesizers,\u201d 34th Irish Signals and Systems Conference (ISSC) (2023) 1 (DOI: 10.1109\/ISSC59246.2023.10162070).","DOI":"10.1109\/ISSC59246.2023.10162070"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Li, <i>et al<\/i>.: \u201cComparative spur performance of a fractional-N frequency synthesizer with a nested MASH-SQ3 divider controller in the presence of memoryless piecewise-linear and polynomial nonlinearities,\u201d 25th IET Irish Signals &amp; Systems Conference 2014 and 2014 China-Ireland International Conference on Information and Communications Technologies (ISSC 2014\/CIICT 2014) (2014) 374 (DOI: 10.1049\/cp.2014.0717).","DOI":"10.1049\/cp.2014.0717"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] D. Mai, <i>et al<\/i>.: \u201cComparison of the simulated performance of two divider controllers in a fractional-N frequency synthesizer with a piecewise-linear charge-pump nonlinearity,\u201d 27th Irish Signals and Systems Conference (ISSC) (2016) 1 (DOI: 10.1109\/ISSC.2016.7528444).","DOI":"10.1109\/ISSC.2016.7528444"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] A. Swaminathan, <i>et al<\/i>.: \u201cA digital requantizer with shaped requantization noise that remains well behaved after nonlinear distortion,\u201d IEEE Trans. Signal Process. <b>55<\/b> (2007) 5382 (DOI: 10.1109\/TSP.2007.899385).","DOI":"10.1109\/TSP.2007.899385"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K.J. Wang, <i>et al<\/i>.: \u201cSpurious tone suppression techniques applied to a wide bandwidth 2.4\u2006GHz fractional-N PLL,\u201d IEEE J. Solid-State Circuits <b>43<\/b> (2008) 2787 (DOI: 10.1109\/JSSC.2008.2005716).","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] E. Familier, <i>et al<\/i>.: \u201cA class of quantizers with DC-free quantization noise and optimal immunity to nonlinearity-induced spurious tones,\u201d IEEE Trans. Signal Process. <b>61<\/b> (2013) 4270 (DOI: 10.1109\/TSP.2013.2263503).","DOI":"10.1109\/TSP.2013.2263503"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] E. Familier and I. Galton: \u201cSecond and third-order noise shaping digital quantizers for low phase noise and nonlinearity-induced spurious tones in fractional-N PLLs,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>63<\/b> (2016) 836 (DOI: 10.1109\/TCSI.2016.2571598).","DOI":"10.1109\/TCSI.2016.2571598"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] D. Mai and M.P. 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Kennedy, <i>et al<\/i>.: \u201c16.9 4.48\u2006GHz 0.18\u2006<i>\u03bc<\/i>m SiGe BiCMOS exact-frequency fractional-N frequency synthesizer with spurious-tone suppression yielding a -80\u2006dBc in-band fractional spur,\u201d ISSCC (2019) 272 (DOI: 10.1109\/ISSCC.2019.8662327).","DOI":"10.1109\/ISSCC.2019.8662327"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y. Donnelly, <i>et al<\/i>.: \u201c4.48-GHz fractional-N frequency synthesizer with spurious-tone suppression via probability mass redistribution,\u201d IEEE Solid-State Circuits Lett. <b>2<\/b> (2019) 264 (DOI: 10.1109\/LSSC.2019.2943936).","DOI":"10.1109\/LSSC.2019.2943936"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Hu, <i>et al<\/i>.: \u201cFractional spurs reduction technique using probability density shaping sigma-delta modulator and fractional frequency divider,\u201d IEEE Trans. Circuits Syst. II, Exp. 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Express <b>19<\/b> (2022) 20220348 (DOI: 10.1587\/elex.19.20220348).","DOI":"10.1587\/elex.19.20220348"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] G. Jin, <i>et al<\/i>.: \u201cA 3.3-4.5\u2006GHz fractional-N sampling PLL with a merged constant slope DTC and sampling PD in 40\u2006nm CMOS,\u201d IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2021) 63 (DOI: 10.1109\/RFIC51843.2021.9490495).","DOI":"10.1109\/RFIC51843.2021.9490495"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Y. 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