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Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/JSSC.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14-bit 2.5\u2006GS\/s and 5\u2006GS\/s RF sampling ADC with background calibration and dither,\u201d VLSI (2016) 1 (DOI: 10.1109\/VLSIC.2016.7573537).","DOI":"10.1109\/VLSIC.2016.7573537"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A.M.A. Ali, <i>et al<\/i>.: \u201cA 12-b 18-GS\/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 3210 (DOI: 10.1109\/JSSC.2020.3023882).","DOI":"10.1109\/JSSC.2020.3023882"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] F. Xu, <i>et al<\/i>.: \u201cA 12-bit 1-GS\/s pipelined ADC with a novel timing strategy in 40-nm CMOS process,\u201d MDPI Electron. <b>12<\/b> (2023) 924 (DOI: 10.3390\/electronics12040924).","DOI":"10.3390\/electronics12040924"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y.-Z. Xi, <i>et al<\/i>.: \u201cAn energy-efficient reconfigurable 18\/12-bit 1\u2006MS\/s pipelined-SAR ADC,\u201d AEU Int. J. Electron. Commun. <b>179<\/b> (2024) 155309 (DOI: 10.1016\/j.aeue.2024.155309).","DOI":"10.1016\/j.aeue.2024.155309"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] L. Fang, <i>et al<\/i>.: \u201cA 12-Bit 1\u2006GS\/s RF sampling pipeline-SAR ADC with harmonic injecting cross-coupled pair achieving 7.5\u2006fj\/conv-step,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 3225 (DOI: 10.1109\/TCSI.2022.3169508).","DOI":"10.1109\/TCSI.2022.3169508"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] B. Vaz, <i>et al<\/i>.: \u201cA 13b 4\u2006GS\/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC,\u201d ISSCC Dig. Tech. Papers (2017) 276 (DOI: 10.1109\/ISSCC.2017.7870368).","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] L. Fang, <i>et al<\/i>.: \u201cA 2.56-GS\/s 12-bit 8x-interleaved ADC with 156.6-dB FoMs in 65-nm CMOS,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>30<\/b> (2022) 123 (DOI: 10.1109\/TVLSI.2021.3133451).","DOI":"10.1109\/TVLSI.2021.3133451"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Q. Yu, <i>et al<\/i>.: \u201cA 12b 8\u2006GS\/s time-interleaved 2\u2006b\/cycle pipelined-SAR ADC with layout-customized bootstrap and super-source-follower based open-loop residue amplifier,\u201d A-SSCC (2022) 1 (DOI: 10.1109\/A-SSCC56115.2022.9980717).","DOI":"10.1109\/A-SSCC56115.2022.9980717"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Devarajan, <i>et al<\/i>.: \u201cA 12-b 10-GS\/s interleaved pipeline ADC in 28-nm CMOS technology,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 3204 (DOI: 10.1109\/JSSC.2017.2747758).","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Y. Chen, <i>et al<\/i>.: \u201cA wide-band input buffer for 3\u2006GS\/s 12\u2006bit time-interleaved ADC,\u201d IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2016) 1467 (DOI: 10.1109\/ICSICT.2016.7998771).","DOI":"10.1109\/ICSICT.2016.7998771"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] C.Y. Chen, <i>et al<\/i>.: \u201cA 12-bit 3\u2006GS\/s pipeline ADC with 0.4\u2006mm<sup>2<\/sup> and 500\u2006mW in 40\u2006nm digital CMOS,\u201d IEEE J. Solid-State Circuits <b>47<\/b> (2012) 1013 (DOI: 10.1109\/JSSC.2012.2185192).","DOI":"10.1109\/JSSC.2012.2185192"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] M. Chen, <i>et al<\/i>.: \u201cA 14\u2006bit 500\u2006MS\/s 85.62\u2006dBc SFDR 66.29\u2006dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40\u2006nm CMOS,\u201d IEICE Electron. Express <b>18<\/b> (2021) 20210171 (DOI: 10.1587\/elex.18.20210171).","DOI":"10.1587\/elex.18.20210171"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] C. Huang, <i>et al<\/i>.: \u201cAn input buffer with 85\u2006dB SFDR for high-speed pipeline ADC,\u201d ICTA (2022) 52 (DOI: 10.1109\/ICTA56932.2022.9962993).","DOI":"10.1109\/ICTA56932.2022.9962993"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] Z. Huang, <i>et al<\/i>.: \u201cLow-voltage high-linearity differential input buffer with current amplifier feed-forward compensation for high-speed ADCs,\u201d ICTA (2020) 41 (DOI: 10.1109\/ICTA50426.2020.9332138).","DOI":"10.1109\/ICTA50426.2020.9332138"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Z. Huang, <i>et al<\/i>.: \u201cA 6-GHz bandwidth input buffer based on AC-coupled flipped source follower for 12-bit 8-GS\/s ADC in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 4163 (DOI: 10.1109\/TCSII.2022.3188534).","DOI":"10.1109\/TCSII.2022.3188534"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] X. Guo, <i>et al<\/i>.: \u201cA 12-bit 2.32\u2006GS\/s pipelined\/SAR hybrid ADC with a high-linearity input buffer,\u201d IEICE Electron. Express <b>20<\/b> (2023) 20230369 (DOI: 10.1587\/elex.20.20230369).","DOI":"10.1587\/elex.20.20230369"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] H. Rapakko and J. Kostamovaara: \u201cOn the performance and use of an improved source-follower buffer,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>54<\/b> (2007) 504 (DOI: 10.1109\/TCSI.2006.887609).","DOI":"10.1109\/TCSI.2006.887609"},{"key":"20","unstructured":"[20] M. Miyahara, <i>et al<\/i>.: \u201cA 10b 320\u2006MS\/s 40\u2006mW open-loop interpolated pipeline ADC,\u201d Symposium on VLSI Circuits IEEE (2011)."},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] H. Lee, <i>et al<\/i>.: \u201cDesign of interpolated pipeline ADC using low-gain open-loop amplifiers,\u201d IEICE Trans. Electron. <b>E96-C<\/b> (2013) 838 (DOI: 10.1587\/transele.E96.C.838).","DOI":"10.1587\/transele.E96.C.838"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] H. Lee, <i>et al<\/i>.: \u201cA 12-bit interpolated pipeline ADC using body voltage controlled amplifier,\u201d 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS) (2013) 1 (DOI: 10.1109\/NEWCAS.2013.6573584).","DOI":"10.1109\/NEWCAS.2013.6573584"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] F. Cao, <i>et al<\/i>.: \u201cAn input buffer for 12\u2006bit 2GS\/s ADC,\u201d ASICON (2017) 750 (DOI: 10.1109\/ASICON.2017.8252584).","DOI":"10.1109\/ASICON.2017.8252584"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Li, <i>et al<\/i>.: \u201cWide-band input buffer with optimized linearity for high-speed high-resolution ADCs,\u201d ASID (2020) 116 (DOI: 10.1109\/ASID50160.2020.9271786).","DOI":"10.1109\/ASID50160.2020.9271786"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] Z. Wu, <i>et al<\/i>.: \u201cAn ADC input buffer with optimized linearity,\u201d IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2018) 1 (DOI: 10.1109\/ICSICT.2018.8564827).","DOI":"10.1109\/ICSICT.2018.8564827"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] Y. Cao, <i>et al<\/i>.: \u201cAn operational amplifier assisted input buffer and an improved bootstrapped switch for high-speed and high-resolution ADCs,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2018) 1 (DOI: 10.1109\/ISCAS.2018.8351071).","DOI":"10.1109\/ISCAS.2018.8351071"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] Y. Yu, <i>et al<\/i>.: \u201cA 12-bit 625\u2006MS\/s time-interleaved pipelined ADC,\u201d International Conference on Integrated Circuits and Microsystems (ICICM) (2023) 538 (DOI: 10.1109\/ICICM59499.2023.10365874).","DOI":"10.1109\/ICICM59499.2023.10365874"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] T. Sun, <i>et al<\/i>.: \u201cA high-linearity input-buffer with high output common-mode stability for 10\u2006bit 3.2\u2006GSs ADC,\u201d Electronics Letters <b>56<\/b> (2020) 634 (DOI: 10.1049\/el.2020.0149).","DOI":"10.1049\/el.2020.0149"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] L. 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