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Wei, <i>et al<\/i>.: \u201cRT-libSGM: FPGA-oriented real-time stereo matching system with high scalability,\u201d IEICE Trans. Inf. &amp; Syst. <b>E106-D<\/b> (2023) 337 (DOI: 10.1587\/transinf.2022EDP7131).","DOI":"10.1587\/transinf.2022EDP7131"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] H. Hirschmuller: \u201cStereo processing by semiglobal matching and mutual information,\u201d IEEE Trans. Pattern Anal. Mach. Intell. <b>30<\/b> (2008) 328 (DOI: 10.1109\/TPAMI.2007.1166).","DOI":"10.1109\/TPAMI.2007.1166"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. LI, <i>et al<\/i>.: \u201cUsing temporal correlation to optimize stereo matching in video sequences,\u201d IEICE Trans. Inf. &amp; Syst. <b>E102-D<\/b> (2019) 1183 (DOI: 10.1587\/transinf.2018EDP7273).","DOI":"10.1587\/transinf.2018EDP7273"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Z. Li, <i>et al<\/i>.: \u201cA 1920 \u00d7 1080 30-frames\/s 2.3\u2006TOPS\/W stereo-depth processor for energy-efficient autonomous navigation of micro aerial vehicles,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 76 (DOI: 10.1109\/JSSC.2017.2751501).","DOI":"10.1109\/JSSC.2017.2751501"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Z. Li, <i>et al<\/i>.: \u201cA 1920 \u00d7 1080 25-frames\/s 2.4-TOPS\/W low-power 6-D vision processor for unified optical flow and stereo depth with semi-global matching,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1048 (DOI: 10.1109\/JSSC.2018.2885559).","DOI":"10.1109\/JSSC.2018.2885559"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y. Lee and H. Kim: \u201cA high-throughput depth estimation processor for accurate semiglobal stereo matching using pipelined inter-pixel aggregation,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>32<\/b> (2022) 411 (DOI: 10.1109\/TCSVT.2021.3061200).","DOI":"10.1109\/TCSVT.2021.3061200"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Z. Li, <i>et al<\/i>.: \u201c3.7 A 1920\u00d71080 30\u2006fps 2.3\u2006TOPS\/W stereo-depth processor for robust autonomous navigation,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) 62 (DOI: 10.1109\/ISSCC.2017.7870261).","DOI":"10.1109\/ISSCC.2017.7870261"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] P. Dong, <i>et al<\/i>.: \u201cA 139\u2006fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching,\u201d 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2021) 1 (DOI: 10.1109\/A-SSCC53895.2021.9634805).","DOI":"10.1109\/A-SSCC53895.2021.9634805"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] Y. Li, <i>et al<\/i>.: \u201cHigh throughput hardware architecture for accurate semi-global matching,\u201d 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (2017) 641 (DOI: 10.1109\/ASPDAC.2017.7858396).","DOI":"10.1109\/ASPDAC.2017.7858396"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] W. Wang, <i>et al<\/i>.: \u201cReal-time high-quality stereo vision system in FPGA,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>25<\/b> (2015) 1696 (DOI: 10.1109\/TCSVT.2015.2397196).","DOI":"10.1109\/TCSVT.2015.2397196"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] F. Schumacher and T. Greiner: \u201cMatching cost computation algorithm and high speed FPGA architecture for high quality real-time semi global matching stereo vision for road scenes,\u201d 17th International IEEE Conference on Intelligent Transportation Systems (ITSC) (2014) 3064 (DOI: 10.1109\/ITSC.2014.6958182).","DOI":"10.1109\/ITSC.2014.6958182"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] X. Zhang, <i>et al<\/i>.: \u201cAlgorithm and VLSI architecture co-design on efficient semi-global stereo matching,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>30<\/b> (2020) 4390 (DOI: 10.1109\/TCSVT.2019.2957275).","DOI":"10.1109\/TCSVT.2019.2957275"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] K. Bong, <i>et al<\/i>.: \u201cA 590\u2006MDE\/s semi-global matching processor with lossless data compression,\u201d 2017 30th IEEE International System-on-Chip Conference (SOCC) (2017) 18 (DOI: 10.1109\/SOCC.2017.8225998).","DOI":"10.1109\/SOCC.2017.8225998"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Lee, <i>et al<\/i>.: \u201cMemory-efficient parametric semiglobal matching,\u201d IEEE Signal Process. Lett. <b>25<\/b> (2018) 194 (DOI: 10.1109\/LSP.2017.2778306).","DOI":"10.1109\/LSP.2017.2778306"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] C.-T. Chang, <i>et al<\/i>.: \u201cHardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching,\u201d Integration <b>92<\/b> (2023) 99 (DOI: 10.1016\/j.vlsi.2023.05.005)","DOI":"10.1016\/j.vlsi.2023.05.005"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] K. Li, <i>et al<\/i>.: \u201cA 320\u2006FPS pixel-level pipelined stereo vision accelerator with regional optimization and multi-direction hole filling,\u201d 2022 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) (2022) 85 (DOI: 10.1109\/PrimeAsia56064.2022.10104009).","DOI":"10.1109\/PrimeAsia56064.2022.10104009"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] D. Mukherjee and S. Mukhopadhyay: \u201cHardware efficient architecture for 2D DCT and IDCT using Taylor-series expansion of trigonometric functions,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>30<\/b> (2020) 2723 (DOI: 10.1109\/TCSVT.2019.2928045).","DOI":"10.1109\/TCSVT.2019.2928045"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] H. Wang, <i>et al<\/i>.: \u201cA 39\u2006pJ\/label 1920x1080 165.7\u2006FPS block patchmatch based stereo matching processor on FPGA,\u201d 2022 IEEE Custom Integrated Circuits Conference (CICC) (2022) 1 (DOI: 10.1109\/CICC53496.2022.9772830).","DOI":"10.1109\/CICC53496.2022.9772830"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] P. Dong, <i>et al<\/i>.: \u201cA 1920\u00d71080 129\u2006fps 4.3\u2006pJ\/pixel stereo-matching processor for pico aerial vehicles,\u201d ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) (2023) 345 (DOI: 10.1109\/ESSCIRC59616.2023.10268790).","DOI":"10.1109\/ESSCIRC59616.2023.10268790"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] O. Rahnama, <i>et al<\/i>.: \u201cReal-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>66<\/b> (2019) 773 (DOI: 10.1109\/TCSII.2019.2909169).","DOI":"10.1109\/TCSII.2019.2909169"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] P. Dong, <i>et al<\/i>.: \u201cA 4.29\u2006nJ\/pixel stereo depth coprocessor with pixel level pipeline and region optimized semi-global matching for IoT application,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 334 (DOI: 10.1109\/TCSI.2021.3100071).","DOI":"10.1109\/TCSI.2021.3100071"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] P. Dong, <i>et al<\/i>.: \u201cConfigurable image rectification and disparity refinement for stereo vision,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>69<\/b> (2022) 3973 (DOI: 10.1109\/TCSII.2022.3191811).","DOI":"10.1109\/TCSII.2022.3191811"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] X. Zhang, <i>et al<\/i>.: \u201cNIPM-sWMF: toward efficient FPGA design for high-definition large-disparity stereo matching,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>29<\/b> (2019) 1530 (DOI: 10.1109\/TCSVT.2018.2833743).","DOI":"10.1109\/TCSVT.2018.2833743"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] Z. Lu, <i>et al<\/i>.: \u201cA resource-efficient pipelined architecture for real-time semi-global stereo matching,\u201d IEEE Trans. Circuits Syst. Video Technol. <b>32<\/b> (2022) 660 (DOI: 10.1109\/TCSVT.2021.3061704).","DOI":"10.1109\/TCSVT.2021.3061704"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] Y. Ma, <i>et al<\/i>.: \u201cPost-processing refinement for semi-global matching algorithm based on real-time FPGA,\u201d 2022 IEEE 35th International System-on-Chip Conference (SOCC) (2022) 1 (DOI: 10.1109\/SOCC56010.2022.9908134).","DOI":"10.1109\/SOCC56010.2022.9908134"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. Wang, <i>et al<\/i>.: \u201cLow-resource hardware architecture for semi-global stereo matching,\u201d 2019 IEEE International Symposium on Circuits and Systems (ISCAS) (2019) 1 (DOI: 10.1109\/ISCAS.2019.8702234).","DOI":"10.1109\/ISCAS.2019.8702234"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] K. Li, <i>et al<\/i>.: \u201cStereo matching accelerator with re-computation scheme and data-reused pipeline for autonomous vehicles,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>71<\/b> (2024) 2760 (DOI: 10.1109\/TCSI.2024.3367186).","DOI":"10.1109\/TCSI.2024.3367186"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] L.F.S. Cambuim, <i>et al<\/i>.: \u201cHardware module for low-resource and real-time stereo vision engine using semi-global matching approach,\u201d 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (2017) 53 (DOI: 10.1145\/3109984.3109992).","DOI":"10.1145\/3109984.3109992"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] S. Shrivastava, <i>et al<\/i>.: \u201cFPGA accelerator for stereo vision using semi-global matching through dependency relaxation,\u201d 2020 30th International Conference on Field-Programmable Logic and Applications (FPL) (2020) 304 (DOI: 10.1109\/FPL50879.2020.00057).","DOI":"10.1109\/FPL50879.2020.00057"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] L.F.S. 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