{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,5]],"date-time":"2026-01-05T22:24:23Z","timestamp":1767651863309,"version":"3.41.0"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,6,25]]},"DOI":"10.1587\/elex.22.20250219","type":"journal-article","created":{"date-parts":[[2025,5,15]],"date-time":"2025-05-15T22:07:30Z","timestamp":1747346850000},"page":"20250219-20250219","source":"Crossref","is-referenced-by-count":1,"title":["Design of hierarchical cache coherence protocol based on Chiplet architecture"],"prefix":"10.1587","volume":"22","author":[{"given":"Jianghua","family":"Gui","sequence":"first","affiliation":[{"name":"School of Microelectronics, Southeast University"},{"name":"China Electronics Technology Group Corporation No.58 Research Institute"}]},{"given":"Bing","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Southeast University"}]},{"given":"Tongtong","family":"Guo","sequence":"additional","affiliation":[{"name":"China Electronics Technology Group Corporation No.58 Research Institute"}]},{"given":"Anzhou","family":"Lai","sequence":"additional","affiliation":[{"name":"China Electronics Technology Group Corporation No.58 Research Institute"}]},{"given":"Shuaishuai","family":"Zhang","sequence":"additional","affiliation":[{"name":"China Electronics Technology Group Corporation No.58 Research Institute"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] W. Tang, <i>et al<\/i>.: \u201cEnergy-efficient parallel interconnects for chiplet integration,\u201d IEEE Micro <b>45<\/b> (2024) 41 (DOI: 10.1109\/MM.2024.3450841).","DOI":"10.1109\/MM.2024.3450841"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] R. Munoz: \u201cFurthering Moore\u2019s law integration benefits in the chiplet era,\u201d IEEE Des. Test <b>41<\/b> (2024) 81 (DOI: 10.1109\/MDAT.2023.3302809).","DOI":"10.1109\/MDAT.2023.3302809"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] C. Li, <i>et al<\/i>.: \u201cAccelerating cache coherence in manycore processor through silicon photonic chiplet,\u201d 2022 IEEE International Conference on Computer-Aided Design (ICCAD) (2022) 1 (DOI: 10.1145\/3508352.354933).","DOI":"10.1145\/3508352.3549338"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] K. Rojaran, <i>et al.<\/i>: \u201cRevisiting the complexity of hardware cache coherence and some implications,\u201d ACM Transactions on Architecture and Code Optimization <b>11<\/b> (2015) 37 (DOI: 10.1145\/2663345).","DOI":"10.1145\/2663345"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Titos-Gil, <i>et al.<\/i>: \u201cWay combination for an adaptive and scalable coherence directory,\u201d IEEE Trans. Parallel Distrib. Syst. <b>30<\/b> (2019) 2608 (DOI: 10.1109\/TPDS.2019.2917185).","DOI":"10.1109\/TPDS.2019.2917185"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] S.H. Gade and S. Deb: \u201cA novel hybrid cache coherence with global snooping for many-core architectures,\u201d ACM Transactions on Design Automation of Electronic Systems <b>27<\/b> (2022) 1 (DOI: 10.1145\/3462775).","DOI":"10.1145\/3462775"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] L. Huang, <i>et al<\/i>.: \u201cIntegrated coherence prediction: Towards efficient cache coherence on noc-based multicore architectures,\u201d ACM Transactions on Design Automation of Electronic Systems <b>19<\/b> (2014) 24 (DOI: 10.1145\/2611756).","DOI":"10.1145\/2611756"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Wang, <i>et al<\/i>.: \u201cResearch on the management strategy of the last level cache sharing multi-core processor,\u201d International Journal of Grid &amp; Distributed Computing <b>8<\/b> (2015) 287 (DOI: 10.14257\/ijgdc.2015.8.5.29).","DOI":"10.14257\/ijgdc.2015.8.5.29"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J. Chang, <i>et al<\/i>.: \u201cThe 65-nm 16-MB shared on-die L3 cache for the dual-core Intel Xeon processor 7100 series,\u201d IEEE J. Solid-State Circuits <b>42<\/b> (2007) 846 (DOI: 10.1109\/JSSC.2007.892185).","DOI":"10.1109\/JSSC.2007.892185"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Fide and S. Jenks: \u201cProactive use of shared L3 caches to enhance cache communications in multi-core processors,\u201d IEEE Comput. Archit. Lett. <b>7<\/b> (2008) 57 (DOI: 10.1109\/L-CA.2008.10).","DOI":"10.1109\/L-CA.2008.10"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M. Huang, <i>et al<\/i>.: \u201cAn energy efficient 32-nm 20-MB shared on-die L3 cache for Intel\u00ae Xeon\u00ae processor E5 family,\u201d IEEE J. Solid-State Circuits <b>48<\/b> (2013) 1954 (DOI: 10.1109\/JSSC.2013.2258815).","DOI":"10.1109\/JSSC.2013.2258815"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S. Naffziger, <i>et al.<\/i>: \u201cPioneering Chiplet technology and design for the AMD EPYC\u2122 and Ryzen\u2122 processor families: industrial product,\u201d 2021 IEEE Annual International Symposium on Computer Architecture (ISCA) (2021) 57 (DOI: 10.1109\/ISCA52012.2021.00014).","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] M. Mattioli: \u201cRome to Milan, AMD continues its tour of Italy,\u201d IEEE Micro <b>41<\/b> (2021) 78 (DOI: 10.1109\/MM.2021.3086541).","DOI":"10.1109\/MM.2021.3086541"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] N. Nassif, <i>et al<\/i>.: \u201cSapphire rapids: the next-generation Intel Xeon scalable processor,\u201d 2022 IEEE International Solid-State Circuits Conference (ISSCC) (2022) 44 (DOI: 10.1109\/ISSCC42614.2022.9731107).","DOI":"10.1109\/ISSCC42614.2022.9731107"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Velten, <i>et al.<\/i>: \u201cMemory performance of AMD EPYC Rome and Intel cascade lake SP server processors,\u201d 2022 ACM\/SPEC International Conference on Performance Engineering (ICPE) (2022) 165 (DOI: 10.1145\/3489525.3511689).","DOI":"10.1145\/3489525.3511689"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] G. Katevenis, <i>et al<\/i>.: \u201cImpact of cache coherence on the performance of shared-memory based MPI primitives: a case study for broadcast on Intel Xeon scalable processors,\u201d 2023 the 52nd International Conference on Parallel Processing (ICPP) (2023) 295 (DOI: 10.1145\/3605573.3605616).","DOI":"10.1145\/3605573.3605616"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] R. Bhargava and K. Troester: \u201cAMD next-generation \u2018Zen 4\u2019 core and 4th Gen AMD EPYC server CPUs,\u201d IEEE Micro <b>44<\/b> (2024) 8 (DOI: 10.1109\/MM.2024.3375070).","DOI":"10.1109\/MM.2024.3375070"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] T. Wang, <i>et al<\/i>.: \u201cApplication defined on-chip networks for heterogeneous Chiplets: an implementation perspective,\u201d 2022 IEEE Symposium on High-Performance Computer Architecture (HPCA) (2022) 1198 (DOI: 10.1109\/HPCA53966.2022.00091).","DOI":"10.1109\/HPCA53966.2022.00091"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S.H. Gade, <i>et al.<\/i>: \u201cScalable hybrid cache coherence using emerging links for chiplet architectures,\u201d 2022 International Conference on VLSI Design (VLSID) (2022) 92 (DOI: 10.1109\/VLSID2022.2022.00029).","DOI":"10.1109\/VLSID2022.2022.00029"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] R. Wang, <i>et al<\/i>.: \u201cDesign of an efficient hybrid cache coherence protocol on Chiplet architecture,\u201d 2024 3rd International Conference on Algorithms, Microchips and Network Applications (AMNA) (2024) 131711 (DOI: 10.1117\/12.3031958).","DOI":"10.1117\/12.3031958"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] S. Naffziger, <i>et al<\/i>.: \u201c2.2 AMD chiplet architecture for high-performance server and desktop products,\u201d 2020 IEEE International Solid-State Circuits Conference (ISSCC) (2020) 44 (DOI: 10.1109\/ISSCC19947.2020.9063103).","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] L.N. Bhuyan, <i>et al<\/i>.: \u201cImpact of CC-NUMA memory management policies on the application performance of multistage switching networks,\u201d IEEE Trans. Parallel Distrib. Syst. <b>11<\/b> (2000) 230 (DOI: 10.1109\/71.841740).","DOI":"10.1109\/71.841740"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] J.D. Booth, <i>et al<\/i>.: \u201cA NUMA-aware version of an adaptive self-scheduling loop scheduler,\u201d ACM Transactions on Architecture and Code Optimization <b>21<\/b> (2024) 4 (DOI: 10.1145\/3680549).","DOI":"10.1145\/3680549"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] H. Nicholson, <i>et al.<\/i>: \u201cChaosity: understanding contemporary NUMA-architectures,\u201d 2023 15th TPC Technology Conference on Performance Evaluation &amp; Benchmarking (TPCTC) (2023) 59 (DOI: 10.1007\/978-3-031-68031-1_5).","DOI":"10.1007\/978-3-031-68031-1_5"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] M.M.K. Martin, <i>et al<\/i>.: \u201cWhy on-chip cache coherence is here to stay,\u201d Communications of the ACM <b>55<\/b> (2012) 78 (DOI: 10.1145\/2209249.2209269).","DOI":"10.1145\/2209249.2209269"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S.M. Khan, <i>et al<\/i>.: \u201cTemporal-based multilevel correlating inclusive cache replacement,\u201d ACM Transactions on Architecture and Code Optimization <b>10<\/b> (2013) 33 (DOI: 10.1145\/2541228.2555290).","DOI":"10.1145\/2555289.2555290"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] H. Grahn and P. Stenstr\u00f6m: \u201cEvaluation of a competitive-update cache coherence protocol with migratory data detection,\u201d Journal of Parallel and Distributed Computing <b>39<\/b> (1996) 168 (DOI: 10.1006\/jpdc.1996.0164).","DOI":"10.1006\/jpdc.1996.0164"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] T. Li and L.K. John: \u201cADir\/sub p\/NB: a cost-effective way to implement full map directory-based cache coherence protocols,\u201d IEEE Trans. Comput. <b>50<\/b> (2001) 921 (DOI: 10.1109\/12.954507).","DOI":"10.1109\/12.954507"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] A.V. Mart\u00ednez: \u201cParallelization of array method with hybrid programming: OpenMP and MPI,\u201d Applied Sciences <b>12<\/b> (2022) 7706 (DOI: 10.3390\/app12157706).","DOI":"10.3390\/app12157706"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] A. Huynh, <i>et al<\/i>.: \u201cUCIe standard: enhancing die-to-die connectivity in modern packaging,\u201d IEEE Micro <b>45<\/b> (2025) 26 (DOI: 10.1109\/MM.2025.3526048).","DOI":"10.1109\/MM.2025.3526048"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] Taballione: \u201cA plug-and-play universal photonic processor for quantum information processing,\u201d 2021 IEEE Hot Chips Symposium (HCS) (2021) 1 (DOI: 10.1109\/HCS52781.2021.9566977).","DOI":"10.1109\/HCS52781.2021.9566977"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/12\/22_22.20250219\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T03:24:54Z","timestamp":1751081094000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/12\/22_22.20250219\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,25]]},"references-count":31,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250219","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,6,25]]},"article-number":"22.20250219"}}