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Li, <i>et al<\/i>.: \u201cA 23.2-to-26\u2006GHz sub-sampling PLL achieving 48.3\u2006fsrms jitter, -253.5\u2006dB FoMJ, and 0.55\u2006<i>\u03bc<\/i>s locking time based on a function-reused VCO-buffer and a type-I FLL with rapid phase alignment,\u201d 2024 IEEE International Solid-State Circuits Conference (ISSCC) (2024) 204 (DOI: 10.1109\/ISSCC49657.2024.10454298).","DOI":"10.1109\/ISSCC49657.2024.10454298"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J. Kim, <i>et al<\/i>.: \u201c16.2 A 76\u2006fsrms jitter and -40\u2006dbc integrated-phase-noise 28-to-31\u2006GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization,\u201d 2019 IEEE International Solid-State Circuits Conference (ISSCC) (2019) 258 (DOI: 10.1109\/ISSCC.2019.8662532).","DOI":"10.1109\/ISSCC.2019.8662532"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] V. 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Wu, <i>et al<\/i>.: \u201cA 28-nm 75-fsrms analog fractional-<i>N<\/i> sampling PLL with a highly linear DTC incorporating background DTC gain calibration and reference clock duty cycle correction,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1254 (DOI: 10.1109\/JSSC.2019.2899726).","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] M. Mercandelli, <i>et al<\/i>.: \u201cA 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 505 (DOI: 10.1109\/JSSC.2021.3123827).","DOI":"10.1109\/JSSC.2021.3123827"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Raj, <i>et al<\/i>.: \u201cA 164\u2006fsrms 9-to-18\u2006GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16\u2006nm FinFET,\u201d 2017 Symposium on VLSI Circuits (VLSIC) (2017) 45 (DOI: 10.23919\/VLSIC.2017.8008474).","DOI":"10.23919\/VLSIC.2017.8008474"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J. Sharma and H. Krishnaswamy: \u201cA 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 1407 (DOI: 10.1109\/JSSC.2018.2889690).","DOI":"10.1109\/JSSC.2018.2889690"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] X. Gao, <i>et al<\/i>.: \u201c9.6 A 2.7-to-4.3\u2006GHz, 0.16\u2006psrms-jitter, -246.8\u2006dB-FOM, digital fractional-N sampling PLL in 28\u2006nm CMOS,\u201d 2016 IEEE International Solid-State Circuits Conference (ISSCC) (2016) 174 (DOI: 10.1109\/ISSCC.2016.7417963).","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Z. Yang, <i>et al<\/i>.: \u201c16.8 A 25.4-to-29.5\u2006GHz 10.2\u2006mW isolated sub-sampling PLL achieving -252.9\u2006dB jitter-power FoM and -63\u2006dBc reference spur,\u201d 2019 IEEE International Solid-State Circuits Conference (ISSCC) (2019) 270 (DOI: 10.1109\/ISSCC.2019.8662364).","DOI":"10.1109\/ISSCC.2019.8662364"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] D.-G. Lee and P.P. Mercier: \u201cA sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of -256\u2006dB,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1542 (DOI: 10.1109\/JSSC.2019.2951377).","DOI":"10.1109\/JSSC.2019.2951377"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] W. Wu, <i>et al<\/i>.: \u201cA 5.5-7.3\u2006GHz analog fractional-N sampling PLL in 28-nm CMOS with 75\u2006fsrms jitter and -249.7\u2006dB FoM,\u201d 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2018) 6403 (DOI: 10.1109\/RFIC.2018.8428844).","DOI":"10.1109\/RFIC.2018.8428844"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M. Mercandelli, <i>et al<\/i>.: \u201cA 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 505 (DOI: 10.1109\/JSSC.2021.3123827).","DOI":"10.1109\/JSSC.2021.3123827"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] Z. Yang, <i>et al<\/i>.: \u201cA 0.003-mm<sup>2<\/sup> 440\u2006fsRMS-jitter and -64\u2006dBc-reference-spur ring-VCO-based type-I PLL using a current-reuse sampling phase detector in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 2307 (DOI: 10.1109\/TCSI.2021.3065462).","DOI":"10.1109\/TCSI.2021.3065462"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] J. Qiu, <i>et al<\/i>.: \u201cA 32-kHz-reference 2.4-GHz fractional-N oversampling PLL with 200-kHz loop bandwidth,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 3741 (DOI: 10.1109\/JSSC.2021.3106514).","DOI":"10.1109\/JSSC.2021.3106514"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] J. Qiu, <i>et al<\/i>.: \u201cA 32\u2006kHz-reference 2.4\u2006GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration,\u201d 2023 IEEE International Solid-State Circuits Conference (ISSCC) (2023) 80 (DOI: 10.1109\/ISSCC42615.2023.10067516).","DOI":"10.1109\/ISSCC42615.2023.10067516"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] E. Helal, <i>et al<\/i>.: \u201cA time amplifier assisted frequency-to-digital converter based digital fractional-<i>N<\/i> PLL,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 2711 (DOI: 10.1109\/JSSC.2020.3048650).","DOI":"10.1109\/JSSC.2020.3048650"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] S. Jang, <i>et al<\/i>.: \u201cA low-jitter and compact-area fractional-N digital PLL with fast multi-variable calibration using the recursive least-squares algorithm,\u201d IEEE J. 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