{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T18:42:39Z","timestamp":1754160159306,"version":"3.41.2"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"14","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,7,25]]},"DOI":"10.1587\/elex.22.20250307","type":"journal-article","created":{"date-parts":[[2025,6,10]],"date-time":"2025-06-10T18:08:03Z","timestamp":1749578883000},"page":"20250307-20250307","source":"Crossref","is-referenced-by-count":0,"title":["High-speed double-error-correction coding scheme for NOR flash memories"],"prefix":"10.1587","volume":"22","author":[{"given":"Yuezhuang","family":"Shi","sequence":"first","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yingnan","family":"Qi","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haiyang","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] R. Bez, <i>et al.<\/i>: \u201cIntroduction to flash memory,\u201d Proc. IEEE <b>91<\/b> (2003) 489 (DOI: 10.1109\/JPROC.2003.811702).","DOI":"10.1109\/JPROC.2003.811702"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] J.E. Brewer and M. Gill: <i>Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using NVM Devices<\/i> (IEEE, 2007) (DOI: 10.1002\/9780470181355).","DOI":"10.1002\/9780470181355"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Y. Wang, <i>et al.<\/i>: \u201cInvestigation on the erase time of Nor Flash,\u201d International Conference on Information Systems and Computer Aided Education (2019) 347 (DOI: 10.1109\/ICISCAE48440.2019.221649).","DOI":"10.1109\/ICISCAE48440.2019.221649"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] T.T.H. Kim: \u201cOverview of memory design for next generation applications,\u201d International SoC Design Conference (2019) 162 (DOI: 10.1109\/ISOCC47750.2019.9027664).","DOI":"10.1109\/ISOCC47750.2019.9027664"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] R. Fastow, <i>et al.<\/i>: \u201cA 45\u2006nm NOR flash technology with self-aligned contacts and 0.024\u2006<i>\u03bc<\/i>m<sup>2<\/sup> cell size for multi-level applications,\u201d International Symposium on VLSI Technology, Systems and Applications (2008) 81 (DOI: 10.1109\/VTSA.2008.4530808).","DOI":"10.1109\/VTSA.2008.4530808"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] G. Campardo, <i>et al.<\/i>: \u201c40-mm\/sup 2\/ 3-V-only 50-MHz 64-Mb 2-b\/cell CHE NOR flash memory,\u201d IEEE J. Solid-State Circuits. <b>35<\/b> (2000) 1655 (DOI: 10.1109\/4.881212).","DOI":"10.1109\/4.881212"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] J. Han, <i>et al.<\/i>: \u201cA critical failure source in 65nm-MLC NOR flash memory incorporating co-salicidation process,\u201d IEEE International Integrated Reliability Workshop Final Report (2006) 80 (DOI: 10.1109\/IRWS.2006.305216).","DOI":"10.1109\/IRWS.2006.305216"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] S. Gregori, <i>et al.<\/i>: \u201cOn-chip error correcting techniques for new-generation flash memories,\u201d Proc. IEEE <b>91<\/b> (2003) 602 (DOI: 10.1109\/JPROC.2003.811709).","DOI":"10.1109\/JPROC.2003.811709"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] R.W. Hamming: \u201cError detecting and error correcting codes,\u201d The Bell System Technical Journal <b>29<\/b> (1950) 147 (DOI: 10.1002\/j.1538-7305.1950.tb00463.x).","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] E. Ou and W. Yang: \u201cFast error-correcting circuits for fault-tolerant memory,\u201d Records of the 2004 International Workshop on Memory Technology, Design and Testing (2004) 8 (DOI: 10.1109\/MTDT.2004.1327977).","DOI":"10.1109\/MTDT.2004.1327977"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] P. Ankolekar, <i>et al.<\/i>: \u201cMultibit error-correction methods for latency-constrained flash memory systems,\u201d IEEE Trans. Device Mater. Rel. <b>10<\/b> (2010) 33 (DOI: 10.1109\/TDMR.2009.2031171).","DOI":"10.1109\/TDMR.2009.2031171"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] R.C. Bose and D.K. Ray-Chaudhuri: \u201cOn a class of error correcting binary group codes,\u201d Information and Control <b>3<\/b> (1960) 68 (DOI: 10.1016\/S0019-9958(60)90287-4).","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] W. Peterson: \u201cEncoding and error-correction procedures for the Bose-Chaudhuri codes,\u201d IRE Transactions on Information Theory <b>6<\/b> (1960) 45 (DOI: 10.1109\/TIT.1960.1057586).","DOI":"10.1109\/TIT.1960.1057586"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] R. Chien: \u201cCyclic decoding procedures for Bose-Chaudhuri-Hocquenghem codes,\u201d IEEE Trans. Inf. Theory <b>10<\/b> (1964) 357 (DOI: 10.1109\/TIT.1964.1053699).","DOI":"10.1109\/TIT.1964.1053699"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] E. Ou and W. Yang: \u201cFast error-correcting circuits for fault-tolerant memory,\u201d Records of the 2004 International Workshop on Memory Technology, Design and Testing (2004) (DOI: 10.1109\/MTDT.2004.1327977).","DOI":"10.1109\/MTDT.2004.1327977"},{"key":"16","unstructured":"[16] Y. Yang, <i>et al.<\/i>: \u201cCircuit design of high-performance BCH decoder with ultra-low latency,\u201d Journal of Harbin Engineering University <b>8<\/b> (2022) 43."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T.H. Chen, <i>et al.<\/i>: \u201cAn adaptive-rate error correction scheme for NAND flash memory,\u201d IEEE VLSI Test Symposium (2009) (DOI: 10.1109\/VTS.2009.24).","DOI":"10.1109\/VTS.2009.24"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] R. Micheloni, <i>et al.<\/i>: \u201cA 4\u2006Gb 2b\/cell NAND flash memory with embedded 5b BCH ECC for 36\u2006MB\/s system read throughput,\u201d IEEE ISSCC Dig. Tech. Papers (2006) 497 (DOI: 10.1109\/ISSCC.2006.1696082).","DOI":"10.1109\/ISSCC.2006.1696082"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] X. Wang, <i>et al.<\/i>: \u201cEmbedded highspeed BCH decoder for new-generation NOR flash memories,\u201d IEEE Custom Integrated Circuits Conference (2009) 195 (DOI: 10.1109\/CICC.2009.5280877).","DOI":"10.1109\/CICC.2009.5280877"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] X. Wang, <i>et al.<\/i>: \u201cA high-speed two-cell BCH decoder for error correcting in MLC NOR flash memories,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>56<\/b> (2009) 865 (DOI: 10.1109\/TCSII.2009.2029144).","DOI":"10.1109\/TCSII.2009.2029144"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] C.C. Chu, <i>et al.<\/i>: \u201cA fully parallel BCH codec with double error correcting capability for NOR flash applications,\u201d IEEE International Conference on Acoustics, Speech and Signal Processing (2012) 1605 (DOI: 10.1109\/ICASSP.2012.6288201).","DOI":"10.1109\/ICASSP.2012.6288201"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] J. Massey: \u201cStep-by-step decoding of the Bose-Chaudhuri-Hocquenghem codes,\u201d IEEE Trans. Inf. Theory <b>11<\/b> (1965) 580 (DOI: 10.1109\/TIT.1965.1053833).","DOI":"10.1109\/TIT.1965.1053833"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] Y. Chen, <i>et al.<\/i>: \u201cA fully-parallel step-by-step BCH decoder over composite field for NOR flash memories,\u201d Proc. Technical Program of 2012 VLSI Design, Automation and Test (2012) 1 (DOI: 10.1109\/VLSI-DAT.2012.6212602).","DOI":"10.1109\/VLSI-DAT.2012.6212602"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] C.L. Chr, <i>et al.<\/i>: \u201cA low-complexity step-by-step decoding algorithm for binary BCH codes,\u201d IEICE Trans. Fundamentals <b>E88-A<\/b> (2005) 359 (DOI: 10.1093\/ietfec\/E88-A.1.359).","DOI":"10.1093\/ietfec\/E88-A.1.359"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] J. Yeon, <i>et al.<\/i>: \u201cLow-complexity triple-error-correcting parallel BCH decoder,\u201d Journal of Semiconductor Technology and Science <b>13<\/b> (2013) 465 (DOI: 10.5573\/JSTS.2013.13.5.465).","DOI":"10.5573\/JSTS.2013.13.5.465"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S.W. Wei: \u201cOn step-by-step complete decoding triple-error-correcting binary BCH codes,\u201d IEICE Trans. Fundamentals <b>E89-A<\/b> (2006) 3360 (DOI: 10.1093\/ietfec\/e89-a.11.3360).","DOI":"10.1093\/ietfec\/e89-a.11.3360"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] E.H. Lu, <i>et al.<\/i>: \u201cA decoding algorithm for triple-error-correcting binary BCH codes,\u201d Information Processing Letters <b>80<\/b> (2001) 299 (DOI: 10.1016\/S0020-0190(01)00180-6).","DOI":"10.1016\/S0020-0190(01)00180-6"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] Z.Y. Xie, <i>et al.<\/i>: \u201cNew decoder for triple-error-correcting binary BCH codes,\u201d IEEE Conference on Industrial Electronics and Applications (2008) 1426 (DOI: 10.1109\/ICIEA.2008.4582754).","DOI":"10.1109\/ICIEA.2008.4582754"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] C.M. Melas: \u201cA cyclic code for double error correction,\u201d IBM Journal of Research and Development <b>4<\/b> (1960) 364 (DOI: 10.1147\/rd.43.0364).","DOI":"10.1147\/rd.43.0364"},{"key":"30","unstructured":"[30] S. Lin and D.J. Costello: <i>Error Control Coding<\/i> (Prentice-Hall, New York, 2004) 2nd ed. 147."},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] M. Shi, <i>et al.<\/i>: \u201cCovering radius of Melas codes,\u201d IEEE Trans. Inf. Theory <b>68<\/b> (2022) 4354 (DOI: 10.1109\/TIT.2022.3152092).","DOI":"10.1109\/TIT.2022.3152092"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/14\/22_22.20250307\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,26]],"date-time":"2025-07-26T04:01:39Z","timestamp":1753502499000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/14\/22_22.20250307\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,25]]},"references-count":31,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250307","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,7,25]]},"article-number":"22.20250307"}}