{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,20]],"date-time":"2026-07-20T18:54:12Z","timestamp":1784573652538,"version":"3.55.0"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"15","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,8,10]]},"DOI":"10.1587\/elex.22.20250317","type":"journal-article","created":{"date-parts":[[2025,6,15]],"date-time":"2025-06-15T18:07:14Z","timestamp":1750010834000},"page":"20250317-20250317","source":"Crossref","is-referenced-by-count":2,"title":["An SRAM-based chunked computing-in-memory macro with a multi-slope voltage-time-digital converting ADC for efficient MAC operations"],"prefix":"10.1587","volume":"22","author":[{"given":"Xiaofeng","family":"Li","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi","family":"Zhan","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhi","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shukao","family":"Dou","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heng","family":"You","sequence":"additional","affiliation":[{"name":"Nanjing Institute of Intelligence Technology"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yumei","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shushan","family":"Qiao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Y. LeCun: \u201cDeep learning &amp; convolutional networks,\u201d IEEE Hot Chips 27 Symposium (HCS) (2015) 1 (DOI: 10.1109\/HOTCHIPS.2015.7477328).","DOI":"10.1109\/HOTCHIPS.2015.7477328"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. He, <i>et al.<\/i>: \u201cDeep residual learning for image recognition,\u201d IEEE Conference on Computer Vision and Pattern Recognition (CVPR) (2016) 770 (DOI: 10.1109\/CVPR.2016.90).","DOI":"10.1109\/CVPR.2016.90"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Horowitz: \u201c1.1 Computing\u2019s energy problem (and what we can do about it),\u201d IEEE International Solid-State Circuits Conference (2014) 10 (DOI: 10.1109\/ISSCC.2014.6757323).","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Kang, <i>et al.<\/i>: \u201cAn energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM,\u201d IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP (2014) 8326 (DOI: 10.1109\/ICASSP.2014.6855225).","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Jeloka, <i>et al.<\/i>: \u201cA 28\u2006nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 1009 (DOI: 10.1109\/JSSC.2016.2515510).","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Zhang, <i>et al.<\/i>: \u201cIn-memory computation of a machine-learn-ing classifier in a standard 6T SRAM array,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 915 (DOI: 10.1109\/JSSC.2016.2642198).","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Tang, <i>et al.<\/i>: \u201cApproxPIM: exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC) (2017) 396 (DOI: 10.1109\/ASPDAC.2017.7858355).","DOI":"10.1109\/ASPDAC.2017.7858355"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L. Jiang, <i>et al.<\/i>: \u201cXNOR-POP: a processing-in-memory architecture for binary convolutional neural networks in wide-IO2 DRAMs,\u201d IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED) (2017) 1 (DOI: 10.1109\/ISLPED.2017.8009163).","DOI":"10.1109\/ISLPED.2017.8009163"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] V. Seshadri, <i>et al.<\/i>: \u201cAmbit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology,\u201d IEEE\/ACM International Symposium on Microarchitecture (MICRO) (2017) 273 (DOI: 10.1145\/3123939.3124544).","DOI":"10.1145\/3123939.3124544"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] P. Chi, <i>et al.<\/i>: \u201cPRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory,\u201d ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (2016) 27 (DOI: 10.1109\/ISCA.2016.13).","DOI":"10.1109\/ISCA.2016.13"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Angizi, <i>et al.<\/i>: \u201cDesign and evaluation of a spintronic in-memory processing platform for nonvolatile data encryption,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. <b>37<\/b> (2018) 1788 (DOI: 10.1109\/TCAD.2017.2774291).","DOI":"10.1109\/TCAD.2017.2774291"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] W. Qiao, <i>et al.<\/i>: \u201cNon-volatile in memory dual-row X(N)OR operation with write back circuit based on 1T1C FeRAM,\u201d IEEE International Conference on Solid-State &amp; Integrated Circuit Technology (ICSICT) (2020) 1 (DOI: 10.1109\/ICSICT49897.2020.9278353).","DOI":"10.1109\/ICSICT49897.2020.9278353"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] C.-J. Jhang, <i>et al.<\/i>: \u201cChallenges and trends of SRAM-based computing-in-memory for AI edge devices,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>68<\/b> (2021) 1773 (DOI: 10.1109\/TCSI.2021.3064189).","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. Yin, <i>et al.<\/i>: \u201cXNOR-SRAM: in-memory computing SRAM macro for binary\/ternary deep neural networks,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1733 (DOI: 10.1109\/JSSC.2019.2963616).","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Z. Jiang, <i>et al.<\/i>: \u201cC3SRAM: an in-memory-computing SRAM macro based on robust capacitive coupling computing mechanism,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1888 (DOI: 10.1109\/JSSC.2020.2992886).","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] H. Kim, <i>et al.<\/i>: \u201cA 1-16b precision reconfigurable digital in-memory computing macro featuring column-MAC architecture and bit-serial computation,\u201d IEEE European Solid State Circuits Conference (ESSCIRC) (2019) 345 (DOI: 10.1109\/ESSCIRC.2019.8902824).","DOI":"10.1109\/ESSCIRC.2019.8902824"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] B. Murmann, \u201cMixed-signal computing for deep neural network inference,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>29<\/b> (2021) 3 (DOI: 10.1109\/TVLSI.2020.3020286).","DOI":"10.1109\/TVLSI.2020.3020286"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] Y.-J. Jo, <i>et al.<\/i>: \u201cTransposable 9T-SRAM computation-in-memory for on-chip learning with probability-based single-slope SAR hybrid ADC for edge devices,\u201d IEEE Solid-State Circuits Lett. <b>6<\/b> (2023) 81 (DOI: 10.1109\/LSSC.2023.3260090).","DOI":"10.1109\/LSSC.2023.3260090"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] J. Lee, <i>et al.<\/i>: \u201cFully row\/column-parallel in-memory compu-ting SRAM macro employing capacitor-based mixed-signal computation with 5-b inputs,\u201d Symposium on VLSI Circuits (2021) 1 (DOI: 10.23919\/VLSICircuits52068.2021.9492444).","DOI":"10.23919\/VLSICircuits52068.2021.9492444"},{"key":"20","unstructured":"[20] X. Si, <i>et al.<\/i>: \u201c15.5 A 28\u2006nm 64\u2006Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,\u201d IEEE International Solid-State Circuits Conference (2020) 246 (DOI: 10.1109\/ISSCC19947.2020.9062995)."},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Z. Yue, <i>et al.<\/i>: \u201cCV-CIM: a hybrid domain xor-derived similarity-aware computation-in-memory supporting cost-volume construction,\u201d IEEE J. Solid-State Circuits <b>60<\/b> (2025) 719 (DOI: 10.1109\/JSSC.2024.3421589).","DOI":"10.1109\/JSSC.2024.3421589"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] J. Mu, <i>et al.<\/i>: \u201cSRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 2412 (DOI: 10.1109\/TCSI.2022.3152653).","DOI":"10.1109\/TCSI.2022.3152653"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] M. Mayahinia, <i>et al.<\/i>: \u201cA voltage-controlled, oscillation-based ADC design for computation-in-memory architectures using emerging ReRAMs,\u201d ACM J. Emerg. Technol. Comput. Syst. <b>18<\/b> (2022) 1 (DOI: 10.1145\/3451212).","DOI":"10.1145\/3451212"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] J. Yue, <i>et al.<\/i>: \u201cAn energy-efficient computing-in-memory NN processor with set-associate blockwise sparsity and ping-pong weight update,\u201d IEEE J. Solid-State Circuits <b>59<\/b> (2024) 1612 (DOI: 10.1109\/JSSC.2023.3324954).","DOI":"10.1109\/JSSC.2023.3324954"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] H. Jia, <i>et al.<\/i>: \u201cScalable and programmable neural network inference accelerator based on in-memory computing,\u201d IEEE J. Solid-State Circuits <b>57<\/b> (2022) 198 (DOI: 10.1109\/JSSC.2021.3119018).","DOI":"10.1109\/JSSC.2021.3119018"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] S. Cheon, <i>et al.<\/i>: \u201cA 2941-TOPS\/W charge-domain 10T SRAM compute-in-memory for ternary neural network,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>70<\/b> (2023) 2085 (DOI: 10.1109\/TCSI.2023.3241385).","DOI":"10.1109\/TCSI.2023.3241385"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] C.-Y. Yao, <i>et al.<\/i>: \u201cA fully bit-flexible computation in memory macro using multi-functional computing bit cell and embedded input sparsity sensing,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 1487 (DOI: 10.1109\/JSSC.2022.3224363).","DOI":"10.1109\/JSSC.2022.3224363"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] B. Zhang, <i>et al.<\/i>: \u201cPIMCA: a programmable in-memory computing accelerator for energy-efficient DNN inference,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 1436 (DOI: 10.1109\/JSSC.2022.3211290).","DOI":"10.1109\/JSSC.2022.3211290"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] K. Zhang, <i>et al.<\/i>: \u201cA charge-domain compute-in-memory macro with cell-embedded DA conversion and two-stage AD conversion for bit-scalable MAC operation,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 1077 (DOI: 10.1109\/TCSII.2023.3322556).","DOI":"10.1109\/TCSII.2023.3322556"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] Q. Zang, <i>et al.<\/i>: \u201c282-to-607 TOPS\/W, 7T-SRAM based CiM with reconfigurable column SAR ADC for neural network processing,\u201d IEEE International Symposium on Circuits and Systems (ISCAS) (2023) 1 (DOI: 10.1109\/ISCAS46773.2023.10181435).","DOI":"10.1109\/ISCAS46773.2023.10181435"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/15\/22_22.20250317\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,16]],"date-time":"2025-08-16T04:15:43Z","timestamp":1755317743000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/15\/22_22.20250317\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,10]]},"references-count":30,"journal-issue":{"issue":"15","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250317","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8,10]]},"article-number":"22.20250317"}}