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Chen, <i>et al<\/i>.: \u201cA 60-Gb\/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>56<\/b> (2021) 750 (DOI: 10.1109\/JSSC.2020.3025285).","DOI":"10.1109\/JSSC.2020.3025285"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Y. Komatsu, <i>et al<\/i>.: \u201cA 0.25-27-Gb\/s PAM4\/NRZ transceiver with adaptive power CDR and jitter analysis,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 2802 (DOI: 10.1109\/JSSC.2019.2920082).","DOI":"10.1109\/JSSC.2019.2920082"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] C. Ahn, <i>et al<\/i>.: \u201cAn 18-Gb\/s NRZ transceiver with a channel-included 2-UI impulse-response filtering FFE and 1-tap DFE compensating up to 32-dB loss,\u201d IEEE Trans. Circuits Syst. II, Exp. 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Verbeke, <i>et al<\/i>.: \u201cA 1.8-pJ\/b, 12.5-25-Gb\/s wide range all-digital clock and data recovery circuit,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 470 (DOI: 10.1109\/JSSC.2017.2755690).","DOI":"10.1109\/JSSC.2017.2755690"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] S. Kang, <i>et al<\/i>.: \u201cA 0.09-pJ\/b\/dB 28-Gb\/s digital CDR with ISI-resistant phase detector,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>71<\/b> (2024) 4618 (DOI: 10.1109\/TCSII.2024.3440584).","DOI":"10.1109\/TCSII.2024.3440584"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Yu, <i>et al<\/i>.: \u201cA 6.5-12.5-Gb\/s half-rate single-loop all-digital referenceless CDR in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 2831 (DOI: 10.1109\/JSSC.2020.3005750).","DOI":"10.1109\/JSSC.2020.3005750"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] T. 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