{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,27]],"date-time":"2025-12-27T04:46:09Z","timestamp":1766810769834,"version":"3.48.0"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"24","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,12,25]]},"DOI":"10.1587\/elex.22.20250409","type":"journal-article","created":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T22:07:20Z","timestamp":1761602840000},"page":"20250409-20250409","source":"Crossref","is-referenced-by-count":0,"title":["BitFleX: Exploiting extreme bit-level sparsity via BTD encoding and dynamic pruning"],"prefix":"10.1587","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-5827-3873","authenticated-orcid":false,"given":"Chendong","family":"Xia","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}]},{"given":"Huidong","family":"Zhao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Qiang","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"}]},{"given":"Shushan","family":"Qiao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences"},{"name":"School of Integrated Circuits, University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] A. 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