{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,15]],"date-time":"2025-11-15T03:29:37Z","timestamp":1763177377034,"version":"3.45.0"},"reference-count":31,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"21","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,11,10]]},"DOI":"10.1587\/elex.22.20250415","type":"journal-article","created":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T22:07:52Z","timestamp":1756764472000},"page":"20250415-20250415","source":"Crossref","is-referenced-by-count":0,"title":["Design of arithmetic units for vector processors based on carbon-based technology"],"prefix":"10.1587","volume":"22","author":[{"given":"Wei","family":"Wu","sequence":"first","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weihua","family":"Zhang","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minghui","family":"Yin","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongwei","family":"Liu","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunxia","family":"You","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huanhuan","family":"Zhou","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Wang","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Baisheng","family":"Peng","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiqiang","family":"Li","sequence":"additional","affiliation":[{"name":"EDA center, Institute of Microelectronics of Chinese Academy of Sciences"},{"name":"University of Chinese Academy of sciences"},{"name":"State Key Lab of Fabrication Technologies for Integrated Circuits"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Y. Wang, <i>et al<\/i>.: \u201c30.6 Vecim: a 289.13\u2006GOPS\/W RISC-V vector co-processor with compute-in-memory vector register file for efficient high-performance computing,\u201d ISSCC <b>67<\/b> (2024) 492 (DOI: 10.1109\/ISSCC49657.2024.10454387).","DOI":"10.1109\/ISSCC49657.2024.10454387"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] N. Kova\u010devi\u0107, <i>et al<\/i>.: \u201cRISC-V vector processor for acceleration of machine learning algorithms,\u201d Telecommunications Forum (TELFOR) (2022) 1 (DOI: 10.1109\/TELFOR56187.2022.9983779).","DOI":"10.1109\/TELFOR56187.2022.9983779"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Barbirotta, <i>et al<\/i>.: \u201cEnhancing fault tolerance in high-performance computing: a real hardware case study on a RISC-V vector processing unit,\u201d IEEE Open J. Comput. Soc. <b>5<\/b> (2024) 553 (DOI: 10.1109\/OJCS.2024.3468895).","DOI":"10.1109\/OJCS.2024.3468895"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] M. Perotti, <i>et al<\/i>.: \u201cSpatzformer: an efficient reconfigurable dual-core RISC-V V cluster for mixed scalar-vector workloads,\u201d 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2024) 172 (DOI: 10.1109\/ASAP61560.2024.00042).","DOI":"10.1109\/ASAP61560.2024.00042"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] M. AskariHemmat, <i>et al<\/i>.: \u201cQuark: an integer RISC-V vector processor for sub-byte quantized DNN inference,\u201d 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (2023) 1 (DOI: 10.1109\/ISCAS46773.2023.10181985).","DOI":"10.1109\/ISCAS46773.2023.10181985"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Marani and A.G. Perri: \u201cReview\u2006\u2014\u2006performance evaluation of CNTFET-based digital circuits: a review,\u201d ECS Journal of Solid State Science and Technology <b>9<\/b> (2020) 051007 (DOI: 10.1149\/2162-8777\/ab9b04).","DOI":"10.1149\/2162-8777\/ab9b04"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M.M. Shulaker, <i>et al<\/i>.: \u201cThree-dimensional integration of nanotechnologies for computing and data storage on a single chip,\u201d Nature <b>547<\/b> (2017) 74 (DOI: 10.1038\/nature22994).","DOI":"10.1038\/nature22994"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L. Liu and Z. Zhang: \u201cCarbon nanotube field-effect transistors: Present and future,\u201d SCIENTIA SINICA Physica, Mechanica &amp; Astronomica <b>46<\/b> (2016) 107305 (DOI: 10.1360\/SSPMA2016-00215).","DOI":"10.1360\/SSPMA2016-00215"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] S. Shreya and R. Chandel: \u201cPerformance analysis of CNTFET based digital logic circuits,\u201d 2014 Students Conference on Engineering and Systems (2014) 1 (DOI: 10.1109\/SCES.2014.6880063).","DOI":"10.1109\/SCES.2014.6880063"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Z. Zhang, <i>et al<\/i>.: \u201cSelf-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage,\u201d Nano Letters <b>8<\/b> (2008) 3696 (DOI: 10.1021\/nl8018802).","DOI":"10.1021\/nl8018802"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M.M. Shulaker, <i>et al<\/i>.: \u201cCarbon nanotube computer,\u201d Nature <b>501<\/b> (2013) 526 (DOI: 10.1038\/nature12502).","DOI":"10.1038\/nature12502"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] B. Rajeshwari, <i>et al<\/i>.: \u201cEdge computing vector processor for CNN applications,\u201d 2024 3rd International Conference on Applied Artificial Intelligence and Computing (ICAAIC) (2024) 293 (DOI: 10.1109\/ICAAIC60222.2024.10574964).","DOI":"10.1109\/ICAAIC60222.2024.10574964"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] M. Perotti, <i>et al<\/i>.: \u201cA \u201cNew Ara\u201d for vector computing: an open source highly efficient RISC-V V 1.0 vector processor design,\u201d 2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2022) 43 (DOI: 10.1109\/ASAP54787.2022.00017).","DOI":"10.1109\/ASAP54787.2022.00017"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] M. Johns and T.J. Kazmierski: \u201cA minimal RISC-V vector processor for embedded systems,\u201d 2020 Forum for Specification and Design Languages (FDL) (2020) 1 (DOI: 10.1109\/FDL50818.2020.9232940).","DOI":"10.1109\/FDL50818.2020.9232940"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Perotti, <i>et al<\/i>.: \u201cYun: an open-source, 64-bit RISC-V-based vector processor with multi-precision integer and floating-point support in 65-nm CMOS,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>70<\/b> (2023) 3732 (DOI: 10.1109\/TCSII.2023.3292579).","DOI":"10.1109\/TCSII.2023.3292579"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] T. Zhao and Z. Ye: \u201cZeroVex: a scalable and high-performance RISC-V vector processor core for embedded systems,\u201d IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2024) 32 (DOI: 10.1109\/ASAP61560.2024.00018).","DOI":"10.1109\/ASAP61560.2024.00018"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] V. Razilov, <i>et al<\/i>.: \u201cDual vector load for improved pipelining in vector processors,\u201d IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) (2023) 1 (DOI: 10.1109\/COOLCHIPS57690.2023.10121996).","DOI":"10.1109\/COOLCHIPS57690.2023.10121996"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] P. Patel and G. Kumar: \u201cOptimization of CNTFET and effect of channel length scaling on CNTFET and MOSFET threshold voltage,\u201d International Conference for Emerging Technology (INCET) (2024) 1 (DOI: 10.1109\/INCET61516.2024.10593374).","DOI":"10.1109\/INCET61516.2024.10593374"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] R. Gupta, <i>et al<\/i>.: \u201cDesign and analysis of 4*4-bit vedic multiplier with 32\u2006nm CNFET technology,\u201d 2023 8th International Conference on Communication and Electronics Systems (ICCES) (2023) 184 (DOI: 10.1109\/ICCES57224.2023.10192881).","DOI":"10.1109\/ICCES57224.2023.10192881"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] A. El-Naggar, <i>et al<\/i>.: \u201cComparative review of carbon nanotube FETs,\u201d Third International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA) (2016) 57 (DOI: 10.1109\/EECEA.2016.7470766).","DOI":"10.1109\/EECEA.2016.7470766"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] M. Islam, <i>et al<\/i>.: \u201cAdvances and significances of carbon nanotube applications: a comprehensive review,\u201d European Polymer Journal <b>220<\/b> (2024) 113443 (DOI: 10.1016\/j.eurpolymj.2024.113443).","DOI":"10.1016\/j.eurpolymj.2024.113443"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] G. Sathish, <i>et al<\/i>.: \u201cCarbon enabled devices in digital era: a predictive performance analysis of CNTFET over Si-NWFET with conventional double gate MOSFET and single gate MOSFET,\u201d 2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE) (2024) 1 (DOI: 10.1109\/IITCEE59897.2024.10486885).","DOI":"10.1109\/IITCEE59897.2024.10486885"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] C.S. Lee, <i>et al<\/i>.: \u201cA compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime\u2006\u2014\u2006Part I: intrinsic elements,\u201d IEEE Trans. Electron Devices <b>62<\/b> (2015) 3061 (DOI: 10.1109\/TED.2015.2457453).","DOI":"10.1109\/TED.2015.2457453"},{"key":"24","unstructured":"[24] \u201cHiCoVec - a configurable SIMD CPU,\u201d (2024) https:\/\/opencores.org\/projects\/hicovec."},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] C.S. Wallace: \u201cA suggestion for a fast multiplier,\u201d IEEE Trans. Electronic Computers <b>13<\/b> (1964) 14 (DOI: 10.1109\/PGEC.1964.263830).","DOI":"10.1109\/PGEC.1964.263830"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] L.T. Clark, <i>et al<\/i>.: \u201cASAP7: A 7-nm finFET predictive process design kit,\u201d Microelectronics Journal <b>53<\/b> (2016) 105 (DOI: 10.1016\/j.mejo.2016.04.006).","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] R.A. Chapman, <i>et al<\/i>.: \u201c0.5 micron CMOS for high performance at 3.3\u2006V,\u201d Technical Digest., International Electron Devices Meeting (1988) 52 (DOI: 10.1109\/IEDM.1988.32748).","DOI":"10.1109\/IEDM.1988.32748"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] L. Peng, <i>et al<\/i>.: \u201cCarbon based nanoelectronics: Materials and devices,\u201d SCIENTIA SINICA Technologica <b>44<\/b> (2014) 1071 (DOI: 10.1360\/N092014-00304).","DOI":"10.1360\/N092014-00304"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] C. Shi, <i>et al<\/i>.: \u201cCNFET-OCL: open-source cell libraries for advanced CNFET technologies,\u201d IEEE Access <b>12<\/b> (2024) 165335 (DOI: 10.1109\/ACCESS.2024.3493625).","DOI":"10.1109\/ACCESS.2024.3493625"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] A. Lazzaz, <i>et al<\/i>.: \u201cPerformance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM, 7 NM and 5 NM node technologies,\u201d Facta universitatis - series: Electronics and Energetics <b>36<\/b> (2023) 1 (DOI: 10.2298\/fuee2301001l).","DOI":"10.2298\/FUEE2301001L"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] P.K. Mahanta, <i>et al<\/i>.: \u201cSkin effect analysis for carbon nano material based interconnects at high frequency,\u201d 2013 International Conference on Informatics, Electronics and Vision (ICIEV) (2013) 17 (DOI: 10.1109\/ICIEV.2013.6572717).","DOI":"10.1109\/ICIEV.2013.6572717"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/21\/22_22.20250415\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,15]],"date-time":"2025-11-15T03:24:46Z","timestamp":1763177086000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/21\/22_22.20250415\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,10]]},"references-count":31,"journal-issue":{"issue":"21","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250415","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,11,10]]},"article-number":"22.20250415"}}