{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,13]],"date-time":"2025-12-13T03:28:07Z","timestamp":1765596487618,"version":"3.48.0"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"23","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2025,12,10]]},"DOI":"10.1587\/elex.22.20250518","type":"journal-article","created":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T22:07:52Z","timestamp":1759961272000},"page":"20250518-20250518","source":"Crossref","is-referenced-by-count":0,"title":["A comma detection and word alignment controller with 8b\/10b decoding function"],"prefix":"10.1587","volume":"22","author":[{"given":"Weishi","family":"Xu","sequence":"first","affiliation":[{"name":"School of Microelectronics, Shanghai University"},{"name":"Shanghai Industrial \u03bc Technology Research Institute"}]},{"given":"Lili","family":"Lang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences"}]},{"given":"Jiang","family":"Zhong","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences"},{"name":"University of Chinese Academy of Sciences"}]},{"given":"Yemin","family":"Dong","sequence":"additional","affiliation":[{"name":"Shanghai Industrial \u03bc Technology Research Institute"},{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences"},{"name":"Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] R. 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ISMVL (2019) (DOI: 10.1109\/ISMVL.2019.00035).","DOI":"10.1109\/ISMVL.2019.00035"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/23\/22_22.20250518\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,13]],"date-time":"2025-12-13T03:26:11Z","timestamp":1765596371000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/22\/23\/22_22.20250518\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,10]]},"references-count":30,"journal-issue":{"issue":"23","published-print":{"date-parts":[[2025]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.22.20250518","relation":{},"ISSN":["1349-2543"],"issn-type":[{"type":"electronic","value":"1349-2543"}],"subject":[],"published":{"date-parts":[[2025,12,10]]},"article-number":"22.20250518"}}