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Kull, <i>et al<\/i>.: \u201c28.5 A 10b 1.5\u2006GS\/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14\u2006nm CMOS FinFET,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) (DOI: 10.1109\/ISSCC.2017.7870467).","DOI":"10.1109\/ISSCC.2017.7870467"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] A.T. Ramkaj, <i>et al<\/i>.: \u201cA 5-GS\/s 158.6-mW 9.4-ENOB passive-sampling time-interleaved three-stage pipelined-SAR ADC with analog-digital corrections in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>55<\/b> (2020) 1553 (DOI: 10.1109\/JSSC.2019.2960476).","DOI":"10.1109\/JSSC.2019.2960476"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] B. Vaz, <i>et al<\/i>.: \u201c16.1 A 13b 4\u2006GS\/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC,\u201d 2017 IEEE International Solid-State Circuits Conference (ISSCC) (2017) (DOI: 10.1109\/ISSCC.2017.7870368).","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Y. Cao, <i>et al<\/i>.: \u201c24.2 A 14b 1\u2006GS\/s single-channel pipelined ADC with a parallel-operation SAR sub-quantizer and a dynamic-deadzone ring amplifier,\u201d 2025 IEEE International Solid-State Circuits Conference (ISSCC) (2025) (DOI: 10.1109\/ISSCC49661.2025.10904766).","DOI":"10.1109\/ISSCC49661.2025.10904766"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] C.Y. Lin, <i>et al<\/i>.: \u201c27.7 A 10b 2.6\u2006GS\/s time-interleaved SAR ADC with background timing-skew calibration,\u201d 2016 IEEE International Solid-State Circuits Conference (ISSCC) (2016) (DOI: 10.1109\/ISSCC.2016.7418110).","DOI":"10.1109\/ISSCC.2016.7418110"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] J.-W. Nam, <i>et al<\/i>.: \u201cA 12-bit 1.6, 3.2, and 6.4\u2006GS\/s 4-b\/cycle time-interleaved SAR ADC with dual reference shifting and interpolation,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1765 (DOI: 10.1109\/JSSC.2018.2808244).","DOI":"10.1109\/JSSC.2018.2808244"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] A.M.A. Ali, <i>et al<\/i>.: \u201cA 14\u2006bit 1\u2006GS\/s RF sampling pipelined ADC with background calibration,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 2857 (DOI: 10.1109\/jssc.2014.2361339).","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] L. Yu, <i>et al<\/i>.: \u201cA 9-bit 1.8\u2006GS\/s 44\u2006mW pipelined ADC using linearized open-loop amplifiers,\u201d IEEE J. Solid-State Circuits <b>51<\/b> (2016) 2210 (DOI: 10.1109\/jssc.2016.2582852).","DOI":"10.1109\/JSSC.2016.2582852"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] R. Sehgal, <i>et al<\/i>.: \u201cA 13-mW 64-dB SNDR 280-MS\/s pipelined ADC using linearized integrating amplifiers,\u201d IEEE J. Solid-State Circuits <b>53<\/b> (2018) 1878 (DOI: 10.1109\/jssc.2018.2815654).","DOI":"10.1109\/JSSC.2018.2815654"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] J. Lagos, <i>et al<\/i>.: \u201cA 1-GS\/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 646 (DOI: 10.1109\/jssc.2018.2889680).","DOI":"10.1109\/JSSC.2018.2889680"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] M. Gu, <i>et al<\/i>.: \u201c24.1 A 12b 3\u2006GS\/s pipelined ADC with gated-LMS-based piecewise- linear nonlinearity calibration,\u201d 2025 IEEE International Solid-State Circuits Conference (ISSCC) 2025 (DOI: 10.1109\/isscc49661.2025.10904536).","DOI":"10.1109\/ISSCC49661.2025.10904536"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] J. Lagos, <i>et al<\/i>.: \u201cA single-channel, 1-GS\/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ\/conv.-step, ringamp-based pipelined ADC with background calibration in 16\u2006nm CMOS,\u201d 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2024) (DOI: 10.1109\/VLSITechnologyandCir46783.2024.10631330).","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631330"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] P. Wang, <i>et al<\/i>.: \u201cA single-channel 8-bit 1.6-GS\/s alternate-comparator SAR ADC with dither-based background offset calibration in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>72<\/b> (2025) 4527 (DOI: 10.1109\/tcsi.2025.3526593).","DOI":"10.1109\/TCSI.2025.3526593"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] M. Gu, <i>et al<\/i>.: \u201cA 1-GS\/s 11-b time-interleaved SAR ADC with robust, fast, and accurate autocorrelation-based background timing-skew calibration,\u201d IEEE J. Solid-State Circuits <b>60<\/b> (2025) 421 (DOI: 10.1109\/jssc.2024.3421363).","DOI":"10.1109\/JSSC.2024.3421363"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Y. Tao, <i>et al<\/i>.: \u201c22.4 A 4.8\u2006GS\/s 7-ENoB time-interleaved SAR ADC with dither-based background timing-skew calibration and bit-distribution-based background ping-pong comparator offset calibration,\u201d 2024 IEEE International Solid-State Circuits Conference (ISSCC) (2024) (DOI: 10.1109\/ISSCC49657.2024.10454299.)","DOI":"10.1109\/ISSCC49657.2024.10454299"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] J. Shen, <i>et al<\/i>.: \u201c24.8 A 12\u2006GS\/s 9b 16\u00d7 time-interleaved SAR ADC in 16\u2006nm FinFET,\u201d 2025 IEEE International Solid-State Circuits Conference (ISSCC) (2025) (DOI: 10.1109\/isscc49661.2025.10904660).","DOI":"10.1109\/ISSCC49661.2025.10904660"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] H. Huang, <i>et al<\/i>.: \u201cA non-interleaved 12-b 330-MS\/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving sub-1-dB SNDR variation,\u201d IEEE J. Solid-State Circuits <b>52<\/b> (2017) 3235 (DOI: 10.1109\/jssc.2017.2732731).","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] S. Hashemi and B. Razavi: \u201cA 7.1\u2006mW 1\u2006GS\/s ADC with 48\u2006dB SNDR at nyquist rate,\u201d IEEE J. Solid-State Circuits <b>49<\/b> (2014) 1739 (DOI: 10.1109\/jssc.2014.2311812).","DOI":"10.1109\/JSSC.2014.2311812"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y. Lim and M.P. Flynn: \u201cA 1\u2006mW 71.5\u2006dB SNDR 50\u2006MS\/s 13\u2006bit fully differential ring amplifier based SAR-assisted pipeline ADC,\u201d IEEE J. Solid-State Circuits <b>50<\/b> (2015) 2901 (DOI: 10.1109\/jssc.2015.2463094).","DOI":"10.1109\/JSSC.2015.2463094"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] K.-J. Moon, <i>et al<\/i>.: \u201cA 9.1-ENOB 6-mW 10-bit 500-MS\/s pipelined-SAR ADC with current-mode residue processing in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits <b>54<\/b> (2019) 2532 (DOI: 10.1109\/jssc.2019.2926648).","DOI":"10.1109\/JSSC.2019.2926648"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] X. Guo, <i>et al<\/i>.: \u201cA 13b 600-675\u2006MS\/s tri-state pipelined-SAR ADC with inverter-based open-loop residue amplifier,\u201d IEEE J. Solid-State Circuits <b>58<\/b> (2023) 624 (DOI: 10.1109\/jssc.2022.3222162).","DOI":"10.1109\/JSSC.2022.3222162"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] N. Li, <i>et al<\/i>.: \u201cA 10-bit 500-MS\/s pipelined SAR ADC with nonlinearity-compensated open-loop amplifier and parallel conversion through comparator reusing,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>72<\/b> (2025) 354 (DOI: 10.1109\/tcsii.2024.3462557).","DOI":"10.1109\/TCSII.2024.3462557"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] L. Fang, <i>et al<\/i>.: \u201cA 12-bit 1\u2006GS\/s RF sampling pipeline-SAR ADC with harmonic injecting cross-coupled pair achieving 7.5\u2006fj\/Conv-Step,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>69<\/b> (2022) 3225 (DOI: 10.1109\/tcsi.2022.3169508).","DOI":"10.1109\/TCSI.2022.3169508"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] L. Fang, <i>et al<\/i>.: \u201cA 12-b 1-GS\/s 61-dB SNDR pipelined-SAR ADC with inverter-based residual amplifier and tunable harmonic-injecting cross-coupled-pair for distortion cancelation achieving 6.3\u2006fJ\/conv-step,\u201d IEEE Solid-State Circuits Lett. <b>5<\/b> (2022) 194 (DOI: 10.1109\/lssc.2022.3193851).","DOI":"10.1109\/LSSC.2022.3193851"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] Y. Shen, <i>et al<\/i>.: \u201cA 12-bit 1.5-GS\/s single-channel pipelined SAR ADC with a pipelined residue amplification stage,\u201d IEEE J. Solid-State Circuits <b>60<\/b> (2025) 260 (DOI: 10.1109\/jssc.2024.3412090).","DOI":"10.1109\/JSSC.2024.3412090"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] Y. Kwon, <i>et al<\/i>.: \u201cA 10-bit 500-MS\/s pipelined SAR ADC with feedback factor compensation in 6-nm FinFET,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs <b>72<\/b> (2025) 698 (DOI: 10.1109\/tcsii.2025.3554297).","DOI":"10.1109\/TCSII.2025.3554297"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] Y. Kwon, <i>et al<\/i>.: \u201cAn 11-bit 360-MS\/s pipelined SAR ADC with feedback factor compensation using a dynamic negative-C-assisted residue amplifier,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers <b>72<\/b> (2025) 3084 (DOI: 10.1109\/tcsi.2024.3496490).","DOI":"10.1109\/TCSI.2024.3496490"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] L. Chen, <i>et al<\/i>.: \u201cMetastable-dither-based digital background calibration of interstage gain nonlinearity in pipelined SAR ADC,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. <b>33<\/b> (2025) 1794 (DOI: 10.1109\/tvlsi.2025.3544825).","DOI":"10.1109\/TVLSI.2025.3544825"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] B. Murmann and B.E. Boser: \u201cA 12-bit 75-MS\/s pipelined ADC using open-loop residue amplification,\u201d IEEE J. Solid-State Circuits <b>38<\/b> (2003) 2040 (DOI: 10.1109\/jssc.2003.819167).","DOI":"10.1109\/JSSC.2003.819167"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] E. Iroaga and B. Murmann: \u201cA 12-bit 75-MS\/s pipelined ADC using incomplete settling,\u201d IEEE J. Solid-State Circuits <b>42<\/b> (2007) 748 (DOI: 10.1109\/JSSC.2007.892154).","DOI":"10.1109\/JSSC.2007.892154"},{"key":"33","doi-asserted-by":"crossref","unstructured":"[33] C.C. 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