{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T04:51:51Z","timestamp":1773463911340,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Electron. Express"],"published-print":{"date-parts":[[2026,3,10]]},"DOI":"10.1587\/elex.23.20250647","type":"journal-article","created":{"date-parts":[[2026,1,20]],"date-time":"2026-01-20T22:09:37Z","timestamp":1768946977000},"page":"20250647-20250647","source":"Crossref","is-referenced-by-count":0,"title":["Analysis and design of aging-resistant strategies for TCFF"],"prefix":"10.1587","volume":"23","author":[{"given":"Yongbo","family":"Cai","sequence":"first","affiliation":[{"name":"School of Microelectronics, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaolong","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingqing","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University"},{"name":"National Integrated Circuit Innovation Center"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Zhu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University"},{"name":"National Integrated Circuit Innovation Center"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] B.G. de Cabiedes, <i>et al<\/i>.: \u201cAn ultra-low-power flip-flop with near-threshold robust operation and redundant-free internal clock transitions,\u201d IEEE Trans. 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Papers <b>67<\/b> (2020) 4761 (DOI: 10.1109\/TCSI.2020.3024601).","DOI":"10.1109\/TCSI.2020.3024601"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/23\/5\/23_23.20250647\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T03:55:45Z","timestamp":1773460545000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/23\/5\/23_23.20250647\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3,10]]},"references-count":30,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2026]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.23.20250647","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3,10]]},"article-number":"23.20250647"}}