{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T05:00:22Z","timestamp":1764997222402},"reference-count":33,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2019,4,1]]},"DOI":"10.1587\/transele.2018cdp0007","type":"journal-article","created":{"date-parts":[[2019,3,31]],"date-time":"2019-03-31T22:10:33Z","timestamp":1554070233000},"page":"287-295","source":"Crossref","is-referenced-by-count":2,"title":["A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications"],"prefix":"10.1587","volume":"E102.C","author":[{"given":"Masanori","family":"HAYASHIKOSHI","sequence":"first","affiliation":[{"name":"Renesas Electronics Corporation"},{"name":"Kanazawa University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"TANIZAKI","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasumitsu","family":"MURAI","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takaharu","family":"TSUJI","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kiyoshi","family":"KAWABATA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"NII","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"},{"name":"Kanazawa University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideyuki","family":"NODA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"},{"name":"Kanazawa University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"KONDO","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoshio","family":"MATSUDA","sequence":"additional","affiliation":[{"name":"Kanazawa University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideto","family":"HIDAKA","sequence":"additional","affiliation":[{"name":"Renesas Electronics Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] T. Nakada, T. Shimizu, and H. Nakamura, \u201cNormally-off Computing for IoT Systems,\u201d ISOCC, pp.147-148, 2015. 10.1109\/isocc.2015.7401761","DOI":"10.1109\/ISOCC.2015.7401761"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Arimoto, T. Yokogawa, and Y. Satoh, \u201cA battery operated normally-off computing technique for energy efficient sensor node applications,\u201d ISOCC, pp.149-150, 2015. 10.1109\/isocc.2015.7401762","DOI":"10.1109\/ISOCC.2015.7401762"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Hayashikoshi, H. Kawai, H. Ueki, and T. Shimizu, \u201cNormally-Off MCU Architecture and Power Management Method for Low-Power Sensor Network,\u201d ISOCC, pp.151-152, 2015. 10.1109\/isocc.2015.7401763","DOI":"10.1109\/ISOCC.2015.7401763"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] T. Kono, T. Ito, T. Tsuruda, T. Nishiyama, T. Nagasawa, T. Ogawa, Y. Kawashima, H. Hidaka, and T. Yamauchi, \u201c40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data,\u201d ISSCC, pp.212-213, 2013. 10.1109\/isscc.2013.6487704","DOI":"10.1109\/ISSCC.2013.6487704"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Y. Taito, M. Nakano, H. Okimoto, D. Okada, T. Ito, T. Kono, K. Noguchi, H. Hidaka, and T. Yamauchi, \u201cA 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB\/s write throughput at Tj, of 170<sup>\u00b0<\/sup>C,\u201d ISSCC, pp.132-133, 2015.","DOI":"10.1109\/ISSCC.2015.7062961"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] H. Mitani, K. Matsubara, H. Yoshida, T. Hashimoto, H. Yamakoshi, S. Abe, T. Kono, Y. Taito, T. Ito, T. Krafuji, K. Noguchi, H. Hidaka, and T. Yamauchi, \u201cA 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ\/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175<sup>\u00b0<\/sup>C,\u201d ISSCC, pp.140-141, 2016. 10.1109\/isscc.2016.7417946","DOI":"10.1109\/ISSCC.2016.7417946"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] M. Ueki, K. Takeuchi, T. Yamamoto, A. Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, H. Sunamura, M. Narihiro, K. Uejima, K.Masuzaki, N. Furutake, S. Saito, Y. Yabe, A. Mitsuiki, K. Takeda, T. Hase, and Y. Hayashi, \u201cLow-Power Embedded ReRAM Technology for IoT Applications,\u201d Symp. On VLSI Technology Dig. Tech Papers, pp.T108-T109, 2015. 10.1109\/vlsit.2015.7223640","DOI":"10.1109\/VLSIT.2015.7223640"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Y. Hayakawa, A. Himeno, R. Yasuhara, W. Boullart, E. Vecchio, T. Vandeweyer, T. Witters, D. Crotti, M. Jurczak, S. Fujii, S. Ito, Y. Kawashima, Y. Ikeda, A. Kawahara, K. Kawai, Z. Wei, S. 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Papers, pp.270-271, 2010. 10.1109\/isscc.2010.5433916","DOI":"10.1109\/ISSCC.2010.5433916"},{"key":"11","unstructured":"[11] R. Ogiwara, D. Takashima, S. Doumae, S. Shiratake, R. Takizawa, and H. Shiga, \u201cHighly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs,\u201d IEEE J. Solid-State Circuits, pp.1324-1331, 2015."},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] M. Qazi, M. Clinton, S. Bartling, and A.P. Chandrakasan, \u201cA low-voltage 1Mb FeRAM in 0.13\u00b5m CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS,\u201d ISSCC Digest of Technical papers, pp.208-210, 2011. 10.1109\/isscc.2011.5746285","DOI":"10.1109\/ISSCC.2011.5746285"},{"key":"13","unstructured":"[13] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski, and K. Kyler, \u201cNonvolatile RAM based on magnetic tunnel junction elements,\u201d ISSCC Digest of Technical papers, pp.130-131, 2000. 10.1109\/isscc.2000.839718"},{"key":"14","unstructured":"[14] T. Tsuji, H. Tanizaki, M. Ishikawa, J. Otani, Y. Yamaguchi, S. Ueno, T. Oishi, and H. Hidaka, \u201cA 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture,\u201d Symp. VLSI Circuits Dig. of Tech. Papers, pp.450-453, 2004. 10.1109\/vlsic.2004.1346647"},{"key":"15","unstructured":"[15] N. Sakimura, T. Sugibayashi, T. Honda, S. Miura, H. Numata, H. Hada, and S. Tahara, \u201cA 512Kb cross-point cell MRAM,\u201d ISSCC Digest of Technical Papers, pp.278-279, 2003. 10.1109\/isscc.2003.1234300"},{"key":"16","unstructured":"[16] Y. Asao, T. Kajiyama, Y. Fukuzumi, M. Amano, H. Aikawa, T. Ueda, T. Kishi, S. Ikegawa, K. Tsuchida, Y. Iwata, A. Nitayama, K. Shimura, Y. Kato, S. Miura, N. Ishiwata, H. Hada, S. Tabara, and H. Yoda, \u201cDesign and Process Integration for High-Density, High-Speed, and Low-Power 6F2 Cross Point MRAM Cell,\u201d IEDM Technical Digest, pp.571-574, 2004. 10.1109\/iedm.2004.1419224"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Jefremow, T. Kern, W. Allers, C. Peters, J. Otterstedt, O. Bahlous, K. Hofmann, R. Allinger, S. Kassenetter, and D. Schmitt-Landsiedel, \u201cTime-differential Sense Amplifier for sub-80mV Bitline Voltage Embedded STT-MRAM in 40nm,\u201d ISSCC, pp.216-217, 2013.","DOI":"10.1109\/ISSCC.2013.6487706"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] T. Andre, S.M. Alam, D. Gogl, C.K. Subramanian, H. Lin, W.Meadows, X. Zhang, N.D. Rizzo, J. Janesky, D. Houssameddine, and J.M. Slaughter, \u201cST-MRAM Fundamentals, Challenges, and Applications,\u201d CICC, pp.1-8, 2013. 10.1109\/cicc.2013.6658449","DOI":"10.1109\/CICC.2013.6658449"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] C. Kim, K. Kwon, C. Park, S. Jang, and J. Choi, \u201cA Covalent-Bonded Cross-Coupled Current-Mode Sense Amplifier for STT-MRAM with 1T1MTJ Common Source-Line Structure Array,\u201d ISSCC, pp.134-135, 2015.","DOI":"10.1109\/ISSCC.2015.7062962"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai, S. Takaya, N. Shimomura, J. Ito, A. Kawasumi, H. Hara, and S. Fujita, \u201cA 3.3ns-Access-Time 71.2\u00b5W\/MHz 1Mb Embedded STT-MRAM Using Physically Eliminated Read-Disturb Scheme and Normally-Off Memory Architecture,\u201d ISSCC, pp.136-137, 2015.","DOI":"10.1109\/ISSCC.2015.7062963"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] J.C. Slonczewski, \u201cCurrent-driven Excitation of Magnetic Multilayers,\u201d J. Magn. Magn. Mater., vol.159, no.1-2, pp.L1-L7, 1996. 10.1016\/0304-8853(96)00062-5","DOI":"10.1016\/0304-8853(96)00062-5"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] W.H. Butler, T. Mewes, C.K.A. Mewes, P.B. Visscher, W.H.Rippard, S.E. Russek, and R. Heindl, \u201cSwitching Distributions for Perpendicular Spin-Torque Devices Within the Macrospin Approximation,\u201d IEEE Trans. Magn., vol.48, no.12, pp.4684-4700, 2012. 10.1109\/tmag.2012.2209122","DOI":"10.1109\/TMAG.2012.2209122"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] J. DeBrosse, T. Maffitt, Y. Nakamura, G. Jan, and P.-K. Wang, \u201cA Fully-Functional 90nm 8Mb STT MRAM Demonstrator Featuring Trimmed, Reference Cell-Based Sensing,\u201d Custom Integrated Circuits Conference (CICC), pp.1-3, 2015. 10.1109\/cicc.2015.7338359","DOI":"10.1109\/CICC.2015.7338359"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, H.Furuta, S. Ueno, T. Oishi, M. Hayashikoshi, and H. Hidaka, \u201cA high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme,\u201d A-SSCC, pp.303-306, Nov. 2006. 10.1109\/asscc.2006.357911","DOI":"10.1109\/ASSCC.2006.357911"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] T.Y. Kim, F. Kimura, Y. Matsui, T. Yoshihara, T. Ooishi, Y. Kihara, and M. Hatanaka, \u201cA 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile\/Robotics Memory System,\u201d A-SSCC, pp.117-120, Nov. 2005.","DOI":"10.1109\/ASSCC.2005.251679"},{"key":"26","unstructured":"[26] H. Kano, K. Bessho, Y. Higo, K. Ohba, M. Hashimoto, T. Mizuguchi, and M. Hosomi, \u201cMRAM with improved magnetic tunnel junction material,\u201d INTERMAG Conf., p.BB-04, 2002."},{"key":"27","unstructured":"[27] R. Scheuerlein, W. Gallagher, S. Parkin, A. Lee, S. Ray, R.Robertazzi, and W. Reohr, \u201cA 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell,\u201d ISSCC Digest of Technical Papers, pp.128-129, 2000. 10.1109\/isscc.2000.839717"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] B.N. Engel, J. Akerman, B. Butcher, R.W. Dave, M. DeHerrera, M. Durlam, G. Grynkewich, J. Janesky, S.V. Pietambaram, N.D. Rizzo, J.M. Slaughter, K. Smith, J.J. Sun, and S. Tehrani, \u201cA 4-Mb Toggle MRAM Based on a Novel Bit and Switching Method,\u201d IEEE Transactions on Magnetics, vol.41, no.1, pp.132-136, 2004.","DOI":"10.1109\/TMAG.2004.840847"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] H. Honigschmid, P. Beer, A. Bette, R. Dittrich, F. Gardic, D. Gogl, S. Lammers, J. Schmid, L. Altimime, S. Bournat, and G. Muller, \u201cSignal-Margin-Screening for Multi-Mb MRAM,\u201d ISSCC Digest of Technical Papers, pp.467-476, 2006.","DOI":"10.1109\/ISSCC.2006.1696079"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, \u201c1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns\/200ps wake-up\/power-off times,\u201d VLSI Circuits (VLSIC), pp.46-47, 2012. 10.1109\/vlsic.2012.6243782","DOI":"10.1109\/VLSIC.2012.6243782"},{"key":"31","doi-asserted-by":"crossref","unstructured":"[31] K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, T. Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, and Y. Watanabe, \u201cA 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes,\u201d ISSCC Digest of Technical Papers, pp.258-259, 2010. 10.1109\/isscc.2010.5433948","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"32","doi-asserted-by":"crossref","unstructured":"[32] C.J. Lin, S.H. Kang, Y.J. Wang, K. Lee, X. Zhu, W.C. Chen, X. Li, W.N. Hsu, Y.C. Kao, M.T. Liu, W.C. Chen, Y. Lin, M. Nowak, N. Yu, and L. Tran, \u201c45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T\/1MTJ Cell,\u201d Electron Devices Meeting (IEDM), pp.1-4, 2009. 10.1109\/iedm.2009.5424368","DOI":"10.1109\/IEDM.2009.5424368"},{"key":"33","unstructured":"[33] S. Chung, K.-M. Rho, S.-D. Kim, H.-J. Suh, D.-J. Kim, H.-J. Kim, S.-H. Lee, J.-H. Park, H.-M. Hwang, S.-M. Hwang, J.-Y. Lee,Y.-B. An, J.-U. Yi, Y.-H. Seo, D.-H. Jung, M.-S. Lee, S.-H. Cho, J.-N. Kim, G.-J. Park, G. Jin, A. Driskill-Smith, V. Nikitin, A. Ong, X. Tang, Y. Kim, J.-S. Rho, S.-K. Park, S.-W. Chung, J.-G. Jeong, and S.-J. Hong, \u201cFully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application,\u201d Electron Devices Meeting (IEDM), pp.12.7.1-12.7.4, 2010. 10.1109\/iedm.2010.5703351"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/4\/E102.C_2018CDP0007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T04:00:26Z","timestamp":1559361626000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/4\/E102.C_2018CDP0007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,1]]},"references-count":33,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2018cdp0007","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4,1]]}}}