{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T19:03:31Z","timestamp":1649012611414},"reference-count":30,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"7","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2019,7,1]]},"DOI":"10.1587\/transele.2018ctp0011","type":"journal-article","created":{"date-parts":[[2019,6,30]],"date-time":"2019-06-30T22:11:23Z","timestamp":1561932683000},"page":"520-529","source":"Crossref","is-referenced-by-count":1,"title":["Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector"],"prefix":"10.1587","volume":"E102.C","author":[{"given":"Zule","family":"XU","sequence":"first","affiliation":[{"name":"The University of Tokyo"}]},{"given":"Anugerah","family":"FIRDAUZI","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology"}]},{"given":"Masaya","family":"MIYAHARA","sequence":"additional","affiliation":[{"name":"High Energy Accelerator Research Organization"}]},{"given":"Kenichi","family":"OKADA","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology"}]},{"given":"Akira","family":"MATSUZAWA","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] N.D. Dalt, \u201cAn Analysis of Phase Noise in Realigned VCOs,\u201d IEEE Trans. Circuits Syst. II Express Briefs, vol.61, no.3, pp.143-147, 2014. 10.1109\/tcsii.2013.2296195","DOI":"10.1109\/TCSII.2013.2296195"},{"key":"2","doi-asserted-by":"publisher","unstructured":"[2] F. Gardner, \u201cCharge-Pump Phase-Lock Loops,\u201d IEEE Trans. Communications, vol.28, no.11, pp.1849-1858, Nov. 1980. 10.1109\/tcom.1980.1094619","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] H. Hedayati, W. Khalil, and B. Bakkaloglu, \u201cA 1 MHz Bandwidth, 6 GHz 0.18 \u00b5m CMOS Type-I \u0394\u03a3 Fractional-N Synthesizer for WiMAX Applications (Vol 44, pg 3244, 2009),\u201d IEEE J. Solid-State Circuits, vol.45, no.6, p.1256, 2010. 10.1109\/jssc.2010.2048616","DOI":"10.1109\/JSSC.2010.2048616"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] S. Shekhar, D. Gangopadhyay, E.-C. Woo, and D.J. Allstot, \u201cA 2.4-GHz Extended-Range Type-I \u03a3\u0394 Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc\/Hz Phase Noise,\u201d IEEE Trans. Circuits Syst. II Express Briefs, vol.58, no.8, pp.472-476, 2011. 10.1109\/tcsii.2011.2158752","DOI":"10.1109\/TCSII.2011.2158752"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A. Sharkia, S. Aniruddhan, S. Shekhar, and S. Mirabbasi, \u201cA high-performance, yet simple to design, digital-friendly type-I PLL,\u201d IEEE CICC2015, vol.2015-Novem, pp.5-8, 2015. 10.1109\/cicc.2015.7338487","DOI":"10.1109\/CICC.2015.7338487"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] L. Kong and B. Razavi, \u201cA 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer,\u201d IEEE J. Solid-State Circuits, vol.51, no.3, pp.626-635, 2016. 10.1109\/jssc.2015.2511157","DOI":"10.1109\/JSSC.2015.2511157"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] L. Kong and B. Razavi, \u201cA 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer,\u201d IEEE J. Solid-State Circuits, vol.52, no.8, pp.2117-2127, 2017. 10.1109\/jssc.2017.2686838","DOI":"10.1109\/JSSC.2017.2686838"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] L. Kong and B. Razavi, \u201cA 2.4-GHz RF Fractional-N Synthesizer With BW=0.25<i>f<\/i><sub>REF<\/sub>,\u201d IEEE J. Solid-State Circuits, vol.53, no.6, pp.1707-1718, 2018. 10.1109\/jssc.2018.2796544","DOI":"10.1109\/JSSC.2018.2796544"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] S.S. Nagam and P.R. Kinget, \u201cA Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation with a Sub-Sampling Phase Detector,\u201d IEEE J. Solid-State Circuits, vol.53, no.3, pp.703-714, 2018. 10.1109\/jssc.2017.2788876","DOI":"10.1109\/JSSC.2017.2788876"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S.S. Nagam and P.R. Kinget, \u201cA 0.008mm<sup>2<\/sup> 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a -239.7dB FoM and -64dBc reference spurs,\u201d in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, pp.1-4, 2018. 10.1109\/cicc.2018.8357091","DOI":"10.1109\/CICC.2018.8357091"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] A. Sharkia, S. Mirabbasi, and S. Shekhar, \u201cA 0.01mm<sup>2<\/sup> 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with -254dB FOM,\u201d in IEEE ISSCC2018, pp.256-258, 2018. 10.1109\/isscc.2018.8310281","DOI":"10.1109\/ISSCC.2018.8310281"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Z. Xu, A. Firdauzi, M. Miyahara, K. Okada, and A. Matsuzawa, \u201cA 2 GHz 3.1 mW type-I digital ring-based PLL,\u201d in IEEE ESSCIRC2016, vol.2016-Octob, pp.205-208, 2016. 10.1109\/esscirc.2016.7598278","DOI":"10.1109\/ESSCIRC.2016.7598278"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] T.K. Kuan and S.I. Liu, \u201cA Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques,\u201d IEEE J. Solid-State Circuits, vol.51, no.4, pp.821-831, 2016. 10.1109\/jssc.2016.2519391","DOI":"10.1109\/JSSC.2016.2519391"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] S. \u00d6l\u00e7er, E. Eleftheriou, and R.A. Hutchins, \u201cCompensation of PLL loop delay in read channels for tape storage systems,\u201d IEEE GLOBECOM2009, no.1, 2009. 10.1109\/glocom.2009.5425364","DOI":"10.1109\/GLOCOM.2009.5425364"},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] L. Vercesi, A. Liscidini, and R. Castello, \u201cTwo-Dimensions Vernier Time-to-Digital Converter,\u201d IEEE J. Solid-State Circuits, vol.45, no.8, pp.1504-1512, 2010. 10.1109\/jssc.2010.2047435","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] M. Lee and A.A. Abidi, \u201cA 9 b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue,\u201d IEEE J. Solid-State Circuits, vol.43, no.4, pp.769-777, April 2008. 10.1109\/jssc.2008.917405","DOI":"10.1109\/JSSC.2008.917405"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[17] M.Z. Straayer and M.H. Perrott, \u201cA Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,\u201d IEEE J. Solid-State Circuits, vol.44, no.4, pp.1089-1098, April 2009. 10.1109\/jssc.2009.2014709","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] H. Liu, D. Tang, Z. Sun, W. Deng, H.C. Ngo, K. Okada, and A. Matsuzawa, \u201cA 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS,\u201d IEEE ISSCC2018, vol.61, pp.246-248, 2018. 10.1109\/isscc.2018.8310276","DOI":"10.1109\/ISSCC.2018.8310276"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] H. Liu, D. Tang, Z. Sun, W. Deng, H.C. Ngo, and K. Okada, \u201cA Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications,\u201d IEEE J. Solid-State Circuits, vol.53, no.12, pp.3540-3552, 2018. 10.1109\/jssc.2018.2878836","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] Z. Xu, S. Lee, M. Miyahara, and A. Matsuzawa, \u201cA 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC,\u201d in IEEE CICC 2013, pp.1-4, 2013. 10.1109\/cicc.2013.6658465","DOI":"10.1109\/CICC.2013.6658465"},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] Z. Xu, M. Miyahara, K. Okada, and A. Matsuzawa, \u201cA 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC,\u201d IEEE J. Solid-State Circuits, vol.51, no.10, pp.2345-2356, 2016. 10.1109\/jssc.2016.2582854","DOI":"10.1109\/JSSC.2016.2582854"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] A. Sai, S. Kondo, T.T. Ta, H. Okuni, M. Furuta, and T. Itakura, \u201cA 65nm CMOS ADPLL with 360\u00b5W 1.6ps-INL SS-ADC-based period-detection-free TDC,\u201d in IEEE ISSCC2016, pp.336-338, 2016. 10.1109\/isscc.2016.7418044","DOI":"10.1109\/ISSCC.2016.7418044"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] T. Siriburanon, S. Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W. Deng, M. Miyahara, K. Okada, and A. Matsuzawa, \u201cA 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture,\u201d IEEE ISSCC Dig. Tech. Pap., vol.58, pp.440-441, 2015. 10.1109\/isscc.2015.7063115","DOI":"10.1109\/ISSCC.2015.7063115"},{"key":"24","doi-asserted-by":"publisher","unstructured":"[24] A.T. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K.K. Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, \u201cA fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -250dB,\u201d IEEE J. Solid-State Circuits, vol.51, no.7, pp.1630-1640, 2016. 10.1109\/jssc.2016.2539344","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] X. Gao, O. Burg, H. Wang, W. Wu, C.-T. Tu, K. Manetakis, F. Zhang, L. Tee, M. Yayla, S. Xiang, R. Tsang, and L. Lin, \u201c9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS,\u201d IEEE ISSCC, San Francisco, pp.174-175, 2016. 10.1109\/isscc.2016.7417963","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"26","doi-asserted-by":"publisher","unstructured":"[26] A.A. Abidi, \u201cPhase noise and jitter in CMOS ring oscillators,\u201d in IEEE J. Solid-State Circuits, vol.41, no.8, pp.1803-1816, 2006. 10.1109\/jssc.2006.876206","DOI":"10.1109\/JSSC.2006.876206"},{"key":"27","doi-asserted-by":"publisher","unstructured":"[27] Z. Xu, S. Lee, M. Miyahara, and A. Matsuzawa, \u201cSub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC,\u201d IEICE Trans. Fundam., vol.E98-A, no.2, pp.476-484, 2015. 10.1587\/transfun.e98.a.476","DOI":"10.1587\/transfun.E98.A.476"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] Y.-C. Huang, C.-F. Liang, H.-S. Huang, and P.-Y. Wang, \u201cA 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO,\u201d in IEEE ISSCC2014, pp.270-271, 2014. 10.1109\/isscc.2014.6757430","DOI":"10.1109\/ISSCC.2014.6757430"},{"key":"29","doi-asserted-by":"publisher","unstructured":"[29] M.S.-W. Chen, D. Su, and S. Mehta, \u201cA calibration-free 800 MHz fractional-N digital PLL with embedded TDC,\u201d IEEE J. Solid-State Circuits, vol.45, no.12, pp.2819-2827, 2010. 10.1109\/jssc.2010.2074950","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] K. Sogo, A. Toya, and T. Kikkawa, \u201cA Ring-VCO-Based Sub-Sampling PLL CMOS Circuit with -119 dBc \/ Hz Phase Noise and 0.73 ps Jitter,\u201d in IEEE ESSCIRC2012, vol.2, no.1, pp.253-256, 2012. 10.1109\/esscirc.2012.6341333","DOI":"10.1109\/ESSCIRC.2012.6341333"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/7\/E102.C_2018CTP0011\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,6]],"date-time":"2019-07-06T03:33:05Z","timestamp":1562383985000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/7\/E102.C_2018CTP0011\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7,1]]},"references-count":30,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2018ctp0011","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,7,1]]}}}