{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,7]],"date-time":"2025-06-07T04:49:32Z","timestamp":1749271772040},"reference-count":25,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2019,4,1]]},"DOI":"10.1587\/transele.2018odi0007","type":"journal-article","created":{"date-parts":[[2019,3,31]],"date-time":"2019-03-31T22:10:41Z","timestamp":1554070241000},"page":"357-363","source":"Crossref","is-referenced-by-count":4,"title":["Recent Progress in the Development of Large-Capacity Integrated Silicon Photonics Transceivers"],"prefix":"10.1587","volume":"E102.C","author":[{"given":"Yu","family":"TANAKA","sequence":"first","affiliation":[{"name":"Photonics Electronics Technology Research Association (PETRA)"},{"name":"Fujitsu Laboratories Limited"},{"name":"Fujitsu Limited"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] A.K. Srivastava, K. Ishii, T. Inoue, and S. Namiki, \u201cToward exa-scale optical circuit switch interconnect networks for future datacenter\/HPC,\u201d Proc. SPIE, vol.10131, pp.1013105-1-8, 2017. 10.1117\/12.2250796"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] M. Al-Fares, A. Loukissas, and A. Vahdat, \u201cA Scalable, Commodity Data Center Network Architecture,\u201d Proc. ACM SIGCOMM 2008 conf. on Data comm., pp.63-74, 2008. 10.1145\/1402958.1402967","DOI":"10.1145\/1402958.1402967"},{"key":"3","unstructured":"[3] Fujitsu white paper, online available; http:\/\/www.fujitsu.com\/global\/Images\/primehpc-fx100-hard-en.pdf"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] I.A. Young, E.M. Mohammed, J.T.S. Liao, A.M. Kern, S. Palermo, B.A. Block, M.R. Reshotko, and P.L.D. Chang, \u201cOptical technology for energy efficient I\/O in high performance computing,\u201d IEEE Commun. Mag., vol.48, no.10, pp.184-191, Oct. 2010. 10.1109\/mcom.2010.5594695","DOI":"10.1109\/MCOM.2010.5594695"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Shalf, S. Dosanjh, and M. Morrison, \u201cExascale Computing Technology Challenges,\u201d VECPAR 2010, LNCS 6449, pp.1-25, 2011. 10.1007\/978-3-642-19328-6_1","DOI":"10.1007\/978-3-642-19328-6_1"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] D. Miller, \u201cDevice requirements for optical interconnects to silicon chips,\u201d Proc. IEEE, vol.97, no.7, pp.1166-1185, 2009. 10.1109\/jproc.2009.2014298","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"7","unstructured":"[7] P. Dobberaere, Proc. ISPEC2017, 2017."},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] C. Doerr, J. Heanue, L. Chen, R. Aroca, S. Azemati, G. Ali, G. McBrien, Li Chen, B. Guan, H. Zhang, X. Zhang, T. Nielsen, H. Mezghani, M. Mihnev, C. Yung, and M. Xu, \u201cSilicon Photonics Coherent Transceiver in a Ball-Grid Array Package,\u201d Proc. OFC2017, Th5D.5, 2017. 10.1364\/ofc.2017.th5d.5","DOI":"10.1364\/OFC.2017.Th5D.5"},{"key":"9","unstructured":"[9] IEEE P802.3bs, 200 Gb\/s and 400 Gb\/s Ethernet Task Force; see; http:\/\/www.ieee802.org\/3\/bs\/"},{"key":"10","unstructured":"[10] Infiniband roadmap, online available; http:\/\/www.infinibandta.org\/content\/pages.php?pg=technology_overview"},{"key":"11","unstructured":"[11] The Consortium for On-Board Optics (COBO), online available; http:\/\/onboardoptics.org\/"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] T. Aoki, S. Sekiguchi, T. Simoyama, S. Tanaka, M. Nishizawa, N. Hatori, Y. Sobu, A. Sugama, T. Akiyama, A. Hayakawa, H. Muranaka, T. Mori, Y. Chen, S.-H. Jeong, Y. Tanaka, and K. Morito, \u201cLow Crosstalk Simultaneous 16-channel \u00d7 25 Gb\/s Operation of High Density Silicon Photonics Optical Transceiveret,\u201d Proc. ECOC, Tu.1.C.3, 2017. 10.1109\/ecoc.2017.8346113","DOI":"10.1109\/ECOC.2017.8346113"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] A. Hayakawa, A. Kibune, A. Toda, S. Tanaka, T. Simoyama, Y. Chen, T. Akiyama, S. Okumura, T. Baba, T. Akahoshi, S. Ueno, K. Maruyama, M. Imai, J.H. Jiang, P. Thachile, T. Riad, S. Sekiguchi, S. Akiyama, Y. Tanaka, K. Morito, D. Mizutani, T. Mori, T. Yamamoto, and H. Ebe, \u201cA 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects,\u201d Proc. OFC, Th1G.2, 2015. 10.1364\/ofc.2015.th1g.2","DOI":"10.1364\/OFC.2015.Th1G.2"},{"key":"14","unstructured":"[14] T. Aoki, S. Sekiguchi, T. Simoyama, S. Tanaka, M. Nishizawa, N. Hatori, Y. Sobu, A. Sugama, T. Akiyama, A. Hayakawa, H. Muranaka, T. Mori, Y. Chen, S.-H. Jeong, Y. Tanaka, and K. Morito, \u201cLow-Crosstalk Simultaneous 16-Channel \u00d7 25 Gb\/s Operation of High-Density Silicon Photonics Optical Transceiver,\u201d J. Lightwave Technol., vol.36, no.5, pp.1262-1267, 2018."},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] S. Tanaka, T. Simoyama, T. Aoki, T. Mori, S. Sekiguchi, S.-H. Jeong, T. Usuki, Y. Tanaka, and K. Morito, \u201cUltra-Low-Power (1.59 mW\/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver,\u201d Proc. ECOC, Th.1.C.1, 2017. 10.1109\/ecoc.2017.8346037","DOI":"10.1109\/ECOC.2017.8346037"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] A. Liu, L. Liao, Y. Chetrit, J. Basak, H. Nguyen, D. Rubin, and M. Paniccia, \u201cWavelength division multiplexing circuit on silicon-on-insulator platform,\u201d IEEE J. Sel. Top. Quantum Electron., vol.16, no.1, pp.23-32, 2010.","DOI":"10.1109\/JSTQE.2009.2033454"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] S. Tanaka, T. Matsumoto, T. Kurahashi, M. Matsuda, A. Uetake, S. Sekiguchi, Y. Tanaka, and K. Morito, \u201cFlip-Chip-Bonded, 8-Wavelength AlGaInAs DFB Laser Array Operable up to 70C for Silicon WDM Interconnects,\u201d Proc. ECOC, Tu.1.1.4, 2014. 10.1109\/ecoc.2014.6963970","DOI":"10.1109\/ECOC.2014.6963970"},{"key":"18","doi-asserted-by":"publisher","unstructured":"[18] S.-H. Jeong, D. Shimura, T. Simoyama, M. Seki, N. Yokoyama, M. Ohtsuka, K. Koshino, T. Horikawa, Y. Tanaka, and K. Morito, \u201cLow-loss, flat-topped and spectrally uniform silicon-nanowire-based 5th-order CROW fabricated by ArF-immersion lithography process on a 300-mm SOI wafer,\u201d Opt. Express, vol.21, no.25, pp.30163-30174, 2013. 10.1364\/oe.21.030163","DOI":"10.1364\/OE.21.030163"},{"key":"19","doi-asserted-by":"publisher","unstructured":"[19] S.-H. Jeong, D. Shimura, T. Simoyama, T. Horikawa, Y. Tanaka, and K. Morito, \u201cSi-nanowire-based multistage delayed Mach-Zehnder interferometer optical MUX\/DeMUX fabricated by an ArF-immersion lithography process on a 300 mm SOI wafer,\u201d Opt. Lett., vol.39, no.13, pp.3702-3705, 2014. 10.1364\/ol.39.003702","DOI":"10.1364\/OL.39.003702"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[20] S.-H. Jeong, Y. Tanaka, and K. Morito, \u201c1 \u00d7 4 Channel Si-Nanowire Microring-Assisted Multiple Delayline-Based Optical MUX\/DeMUX,\u201d J. Lightwave Technol., vol.33, no.17, pp.3736-3743, 2015. 10.1109\/jlt.2015.2457431","DOI":"10.1109\/JLT.2015.2457431"},{"key":"21","unstructured":"[21] Y. Sobu, S.-H. Jeong, Y. Tanaka, and K. Morito, \u201c300 mm ArF-immersion lithography technology based Si-wire grating couplers with high coupling efficiency and low crosstalk,\u201d Proc. OECC 2016, TuE.4.3, 2016."},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] S.-H. Jeong, Y. Sobu, S. Tanaka, T, Simoyama, Y. Tanaka, and K. Morito, \u201cWDM Interconnect targeted Si-wire demultiplexers for large manufacturing tolerance, low voltage tunability & polarization diversified operability,\u201d Proc. OFC 2016, Tu2F.6, 2016. 10.1364\/ofc.2016.tu2f.6","DOI":"10.1364\/OFC.2016.Tu2F.6"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[23] S. Tanaka, T. Simoyama, T. Aoki, T. Mori, S. Sekiguchi, S.-H. Jeong, T. Usuki, Y. Tanaka, and K. Morito, \u201cUltralow-Power (1.59 mW\/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver,\u201d J. Lightwave Technol., vol.36, no.5, pp.1275-1280, 2018. 10.1109\/jlt.2018.2799965","DOI":"10.1109\/JLT.2018.2799965"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] T. Akiyama, T. Aoki, T. Simoyama1, A. Sugama, S. Sekiguchi, Y. Sobu, S. Tanaka, Y. Tanaka, S.-H. Jeong, M. Nishizawa, N. Hatori, A. Hayakawa, T. Mori, \u201cError-Free Loopback of a Compact 25 Gb\/s \u00d7 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction,\u201d Proc. OFC, Tu.1.1.4, 2018. 10.1364\/ofc.2018.w1i.2","DOI":"10.1364\/OFC.2018.W1I.2"},{"key":"25","doi-asserted-by":"publisher","unstructured":"[25] J.V. Campenhout, W. Green, and Y.A. Vlasov, \u201cDesign of a digital, ultra-broadband electro-optic switch for reconfigurable optical networks-on-chip,\u201d Opt. Express, vol.17, no.26, pp.24020-24029, 2009. 10.1364\/oe.17.023793","DOI":"10.1364\/OE.17.023793"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/4\/E102.C_2018ODI0007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T04:03:20Z","timestamp":1559361800000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E102.C\/4\/E102.C_2018ODI0007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,1]]},"references-count":25,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2018odi0007","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4,1]]}}}