{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,19]],"date-time":"2025-10-19T06:08:36Z","timestamp":1760854116265},"reference-count":23,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2020,4,1]]},"DOI":"10.1587\/transele.2019cdp0007","type":"journal-article","created":{"date-parts":[[2020,3,31]],"date-time":"2020-03-31T22:16:43Z","timestamp":1585693003000},"page":"144-152","source":"Crossref","is-referenced-by-count":2,"title":["Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters"],"prefix":"10.1587","volume":"E103.C","author":[{"given":"Kentaro","family":"KOJIMA","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kodai","family":"YAMADA","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"FURUTA","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazutoshi","family":"KOBAYASHI","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Kyoto Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] H. Miyazaki, Y. Kusano, H. Okano, T. Nakada, K. Seki, T. Shimizu, N. Shinjo, F. Shoji, A. Uno, and M. Kurokawa, \u201cK computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores,\u201d 2012 IEEE Int. Solid-State Circuits Conf. (ISSCC), pp.192-194, Feb. 2012. 10.1109\/isscc.2012.6176971","DOI":"10.1109\/ISSCC.2012.6176971"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] D. Krueger, E. Francom, and J. Langsdorf, \u201cCircuit design for voltage scaling and SER immunity on a quad-core itanium processor,\u201d 2008 IEEE Int. Solid-State Circuits Conf., pp.94-95, Feb. 2008. 10.1109\/isscc.2008.4523073","DOI":"10.1109\/ISSCC.2008.4523073"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] N. Seifert, B. Gill, K. Foley, and P. Relangi, \u201cMulti-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments,\u201d 2008 IEEE Int. Rel. Physics Symp., pp.181-186, 2008. 10.1109\/relphy.2008.4558882","DOI":"10.1109\/RELPHY.2008.4558882"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K. Kim, \u201cCombinational logic soft error correction,\u201d 2006 IEEE Int. Test Conf., pp.824-832, Oct. 2006. 10.1109\/test.2006.297681","DOI":"10.1109\/TEST.2006.297681"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Furuta, K. Kobayashi, and H. Onodera, \u201cImpact of cell distance and well-contact density on neutron-induced multiple cell upsets,\u201d 2013 IEEE Int. Rel. Physics Symp., pp.6C.3.1-6C.3.4, 2013. 10.1109\/irps.2013.6532053","DOI":"10.1109\/IRPS.2013.6532053"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] K. Kobayashi, K. Kubota, M. Masuda, Y. Manzawa, J. Furuta, S. Kanda, and H. Onodera, \u201cA low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI,\u201d IEEE Trans. Nucl. Sci., vol.61, no.4, pp.1881-1888, Aug. 2014. 10.1109\/tns.2014.2318326","DOI":"10.1109\/TNS.2014.2318326"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] P.E. Dodd, A.R. Shaneyfelt, K.M. Horn, D.S. Walsh, G.L. Hash, T.A. Hill, B.L. Draper, J.R. Schwank, F.W. Sexton, and P.S. Winokur, \u201cSEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments,\u201d IEEE Trans. Nucl. Sci., vol.48, no.6, pp.1893-1903, Dec. 2001. 10.1109\/23.983148","DOI":"10.1109\/23.983148"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] K. Hirose, H. Saito, Y. Kuroda, S. Ishii, Y. Fukuoka, and D. Takahashi, \u201cSEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design,\u201d IEEE Trans. Nucl. Sci., vol.49, no.6, pp.2965-2968, Dec. 2002. 10.1109\/tns.2002.805978","DOI":"10.1109\/TNS.2002.805978"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] P. Roche, G. Gasiot, K. Forbes, V. O'Sullivan, and V. Ferlet, \u201cComparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node,\u201d IEEE Trans. Nucl. Sci., vol.50, no.6, pp.2046-2054, Dec. 2003. 10.1109\/tns.2003.821588","DOI":"10.1109\/TNS.2003.821588"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] G. Gasiot, P. Roche, and P. Flatresse, \u201cComparison of multiple cell upset response of BULK and SOI 130nm technologies in the terrestrial environment,\u201d 2008 IEEE Int. Rel. Physics Symp., pp.192-194, 2008. 10.1109\/relphy.2008.4558884","DOI":"10.1109\/RELPHY.2008.4558884"},{"key":"11","doi-asserted-by":"publisher","unstructured":"[11] M. Raine, M. Gaillardin, T. Lagutere, O. Duhamel, and P. Paillet, \u201cEstimation of the single-event upset sensitivity of advanced SOI SRAMs,\u201d IEEE Trans. Nucl. Sci., vol.65, no.1, pp.339-345, Jan. 2018. 10.1109\/tns.2017.2779786","DOI":"10.1109\/TNS.2017.2779786"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] A. Makihara, T. Yamaguchi, Y. Tsuchiya, T. Arimitsu, H. Asai, Y. Iide, H. Shindou, S. Kuboyama, and S. Matsuda, \u201cSee in a 0.15 \/spl mu\/m fully depleted CMOS\/SOI commercial process,\u201d IEEE Trans. Nucl. Sci., vol.51, no.6, pp.3621-3625, Dec. 2004. 10.1109\/tns.2004.839155","DOI":"10.1109\/TNS.2004.839155"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[14] Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, and S. Kimura, \u201cSmallest vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate,\u201d 2008 Symposium on VLSI Technology, pp.166-167, June 2008. 10.1109\/vlsit.2008.4588604","DOI":"10.1109\/VLSIT.2008.4588604"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[15] P. Roche, J.-L. Autran, G. Gasiot, and D. Munteanu, \u201cTechnology downscaling worsening radiation effects in bulk: Soi to the rescue,\u201d 2013 IEEE International Electron Devices Meeting, pp.31.1.1-31.1.4, Dec. 2013. 10.1109\/iedm.2013.6724728","DOI":"10.1109\/IEDM.2013.6724728"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[16] F. Liu, I. Ionica, M. Bawedin, and S. Cristoloveanu, \u201cEffect of back gate on parasitic bipolar effect in FD SOI MOSFETs,\u201d 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp.1-2, Oct. 2014. 10.1109\/s3s.2014.7028210","DOI":"10.1109\/S3S.2014.7028210"},{"key":"16","doi-asserted-by":"publisher","unstructured":"[17] K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi, \u201cRadiation-hardened flip-flops with low-delay overhead using pMOS pass-transistors to suppress SET pulses in a 65-nm FDSOI process,\u201d IEEE Trans. Nucl. Sci., vol.65, no.8, pp.1814-1822, Aug. 2018. 10.1109\/tns.2018.2826726","DOI":"10.1109\/TNS.2018.2826726"},{"key":"17","doi-asserted-by":"publisher","unstructured":"[18] A. Makihara, M. Midorikawa, T. Yamaguchi, Y. Iide, T. Yokose, Y. Tsuchiya, T. Arimitsu, H. Asai, H. Shindou, S. Kuboyama, and S. Matsuda, \u201cHardness-by-design approach for 0.15 \u00b5m fully depleted CMOS\/SOI digital logic devices with enhanced SEU\/SET immunity,\u201d IEEE Trans. Nucl. Sci., vol.52, no.6, pp.2524-2530, Dec. 2005. 10.1109\/tns.2005.860716","DOI":"10.1109\/TNS.2005.860716"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[19] B. Narasimham, J.K. Wang, N. Vedula, S. Gupta, B. Bartz, C. Monzel, I. Chatterjee, B.L. Bhuva, R.D. Schrimpf, and R.A. Reed, \u201cInfluence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs,\u201d 2015 IEEE International Reliability Physics Symposium, pp.2C.4.1-2C.4.5, April 2015. 10.1109\/irps.2015.7112679","DOI":"10.1109\/IRPS.2015.7112679"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[20] A. Evans, D. Alexandrescu, V. Ferlet-Cavrois, and K.-O. Voss, \u201cTechniques for heavy ion microbeam analysis of FPGA SER sensitivty,\u201d 2015 IEEE International Reliability Physics Symposium, pp.SE.6.1-SE.6.6, April 2015. 10.1109\/irps.2015.7112826","DOI":"10.1109\/IRPS.2015.7112826"},{"key":"20","doi-asserted-by":"publisher","unstructured":"[21] H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi, \u201cA low-power radiation-hardened flip-flop with stacked transistors in a 65 nm FDSOI process,\u201d IEICE Trans. Electron., vol.E101-C, no.4, pp.273-280, 2018. 10.1587\/transele.e101.c.273","DOI":"10.1587\/transele.E101.C.273"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[22] J.S. Kauppila, T.D. Loveless, R.C. Quinn, J.A. Maharrey, M.L. Alles, M.W. McCurdy, R.A. Reed, B.L. Bhuva, L.W. Massengill, and K. Lilja, \u201cUtilizing device stacking for area efficient hardened SOI flip-flop designs,\u201d 2014 IEEE International Reliability Physics Symposium (IRPS), pp.SE.4.1-SE.4.7, June 2014. 10.1109\/irps.2014.6861176","DOI":"10.1109\/IRPS.2014.6861176"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[23] C.-W. Tsai, M.-C. Chen, S.-H. Ku, and T. Wang, \u201cAuger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias,\u201d IEEE Trans. Electron Devices, vol.50, no.4, pp.1022-1026, April 2003. 10.1109\/ted.2003.812484","DOI":"10.1109\/TED.2003.812484"},{"key":"23","doi-asserted-by":"publisher","unstructured":"[24] S.-D. Kim, C.-M. Park, and J.C.S. Woo, \u201cAdvanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. theoretical derivation,\u201d IEEE Trans. Electron Devices, vol.49, no.3, pp.457-466, March 2002. 10.1109\/16.987117","DOI":"10.1109\/16.987117"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/4\/E103.C_2019CDP0007\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,4]],"date-time":"2020-04-04T03:27:57Z","timestamp":1585970877000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/4\/E103.C_2019CDP0007\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,1]]},"references-count":23,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2019cdp0007","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4,1]]}}}