{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,10,7]],"date-time":"2022-10-07T00:14:05Z","timestamp":1665101645434},"reference-count":20,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2020,5,1]]},"DOI":"10.1587\/transele.2019ecp5008","type":"journal-article","created":{"date-parts":[[2019,11,26]],"date-time":"2019-11-26T22:04:26Z","timestamp":1574805866000},"page":"263-273","source":"Crossref","is-referenced-by-count":0,"title":["A Highly Configurable 7.62GOP\/s Hardware Implementation for LSTM"],"prefix":"10.1587","volume":"E103.C","author":[{"given":"Yibo","family":"FAN","sequence":"first","affiliation":[{"name":"State Kay Lab of ASIC & System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leilei","family":"HUANG","sequence":"additional","affiliation":[{"name":"State Kay Lab of ASIC & System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kewei","family":"CHEN","sequence":"additional","affiliation":[{"name":"State Kay Lab of ASIC & System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyang","family":"ZENG","sequence":"additional","affiliation":[{"name":"State Kay Lab of ASIC & System, Fudan University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] M. Sundermeyer, R. Schl\u00fcter, and H. Ney, \u201cLSTM neural networks for language modeling,\u201d Thirteenth Annual Conference of the International Speech Communication Association, 2012.","DOI":"10.21437\/Interspeech.2012-65"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] A. Graves, N. Jaitly, and A.-R. Mohamed, \u201cHybrid speech recognition with deep bidirectional lstm,\u201d 2013 IEEE Workshop on Automatic Speech Recognition and Understanding (ASRU), IEEE, pp.273-278, 2013. 10.1109\/asru.2013.6707742","DOI":"10.1109\/ASRU.2013.6707742"},{"key":"3","doi-asserted-by":"publisher","unstructured":"[3] J. Cheng, P.-S. Wang, G. Li, Q.-H. Hu, and H.-Q. Lu, \u201cRecent advances in efficient computation of deep convolutional neural networks,\u201d Frontiers of Information Technology & Electronic Engineering, vol.19, no.1, pp.64-77, 2018. 10.1631\/fitee.1700789","DOI":"10.1631\/FITEE.1700789"},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] S. Hochreiter and J. Schmidhuber, \u201cLong short-term memory,\u201d Neural Computation, vol.9, no.8, pp.1735-1780, 1997. 10.1162\/neco.1997.9.8.1735","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] F.A. Gers and J. Schmidhuber, \u201cRecurrent nets that time and count,\u201d Proc. IEEE-INNS-ENNS International Joint Conference on Neural Network (IJCNN), vol.III, pp.189-194, IEEE, 2000. 10.1109\/ijcnn.2000.861302","DOI":"10.1109\/IJCNN.2000.861302"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] F.A. Gers, J. Schmidhuber, and F. Cummins, \u201cLearning to forget: Continual prediction with LSTM,\u201d Proc. International Conference on Artificial Neural Networks (ICANN), vol.II, pp.850-855, 1999.","DOI":"10.1049\/cp:19991218"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] K. Greff, R.K. Srivastava, J. Koutnik, B.R. Steunebrink, and J. Schmidhuber, \u201cLstm: A search space odyssey,\u201d IEEE Trans. Neural Netw. Learn. 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Fonseca, \u201cAn FPGA implementation of a long short-term memory neural network,\u201d Proc. IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.1-8, 2017.","DOI":"10.1109\/ReConFig.2016.7857151"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Y. Guan, Z. Yuan, G. Sun, and J. Cong, \u201cFpga-based accelerator for long short-term memory recurrent neural networks,\u201d Proc. 22nd Asia and South Pacific Design Automation Conference (ASPDAC), IEEE, pp.629-634, 2017. 10.1109\/aspdac.2017.7858394","DOI":"10.1109\/ASPDAC.2017.7858394"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Y. Zhang, C. Wang, L. Gong, Y. Lu, F. Sun, C. Xu, X. Li, and X. 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International Symposium on Field-Programmable Gate Arrays (FPGA), ACM, pp.75-84, 2017."},{"key":"19","unstructured":"[19] J. Liu, J. Wang, Y. Zhou, and F. Liu, \u201cA cloud server oriented FPGA accelerator for LSTM recurrent neural network,\u201d IEEE Access, vol.7, pp.122408-122418, 2019."},{"key":"20","unstructured":"[20] K. Khalil, O. Eldash, A. Kumar, and M. Bayoumi, \u201cEconomic LSTM approach for recurrent neural networks,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.66, no.11, pp.1885-1889, Nov. 2019."}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/5\/E103.C_2019ECP5008\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,6]],"date-time":"2022-10-06T23:54:40Z","timestamp":1665100480000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/5\/E103.C_2019ECP5008\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5,1]]},"references-count":20,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2019ecp5008","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,5,1]]}}}