{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T03:04:20Z","timestamp":1648868660333},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2020,3,1]]},"DOI":"10.1587\/transele.2019lhp0010","type":"journal-article","created":{"date-parts":[[2020,2,29]],"date-time":"2020-02-29T22:05:32Z","timestamp":1583013932000},"page":"98-109","source":"Crossref","is-referenced-by-count":0,"title":["Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler"],"prefix":"10.1587","volume":"E103.C","author":[{"given":"Yoshitake","family":"OKI","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Yuto","family":"ABE","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Kazuki","family":"YAMAMOTO","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Kohei","family":"YAMAMOTO","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Tomoya","family":"SHIRAKAWA","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Akimasa","family":"YOSHIDA","sequence":"additional","affiliation":[{"name":"School of Interdisciplinary Mathematical Sciences, Meiji University"}]},{"given":"Keiji","family":"KIMURA","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]},{"given":"Hironori","family":"KASAHARA","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Waseda University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] J. Sj\u00f6din and C. von Platen, \u201cStorage allocation for embedded processors,\u201d Proc. 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.15-23, ACM, 2001. 10.1145\/502217.502221","DOI":"10.1145\/502217.502221"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] O. Ozturk, M. Kandemir, M.J. Irwin, and S. Tosun, \u201cMulti-level on-chip memory hierarchy design for embedded chip multiprocessors,\u201d 12th International Conference on Parallel and Distributed Systems, ICPADS&apos;06, 2006. 10.1109\/icpads.2006.66","DOI":"10.1109\/ICPADS.2006.66"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] M. Kandemir, J. Ramanujam, and A. Choudhary, \u201cExploiting shared scratch pad memory space in embedded multiprocessor systems,\u201d Proc. 39th Annual Design Automation Conference, DAC&apos;02, New York, NY, USA, pp.219-224, ACM, 2002. 10.1145\/513918.513974","DOI":"10.1145\/513918.513974"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] I. Issenin, E. Brockmeyer, B. Durinck, and N. Dutt, \u201cMultiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies,\u201d 43rd ACM\/IEEE Design Automation Conference, pp.49-52, July 2006. 10.1145\/1146909.1146925","DOI":"10.1145\/1146909.1146925"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] V. Suhendra, C. Raghavan, and T. Mitra, \u201cIntegrated scratchpad memory optimization and task scheduling for MPSoC architectures,\u201d Proc. 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp.401-410, ACM, 2006. 10.1145\/1176760.1176809","DOI":"10.1145\/1176760.1176809"},{"key":"6","unstructured":"[6] L. Li, L. Gao, and J. Xue, \u201cMemory coloring: A compiler approach for scratchpad memory management,\u201d 14th International Conference on Parallel Architectures and Compilation Techniques, PACT 2005, pp.329-338, IEEE, 2005. 10.1109\/pact.2005.27"},{"key":"7","unstructured":"[7] P.R. Panda, N.D. Dutt, and A. Nicolau, \u201cEfficient utilization of scratch-pad memory in embedded processor applications,\u201d Proc. 1997 European Conference on Design and Test, EDTC&apos;97, Washington, DC, USA, pp.7-11, IEEE, 1997. 10.1109\/edtc.1997.582323"},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] O. Avissar, R. Barua, and D. Stewart, \u201cAn optimal memory allocation scheme for scratch-pad-based embedded systems,\u201d ACM Trans. Embed. Comput. Syst., vol.1, no.1, pp.6-26, Nov. 2002. 10.1145\/581888.581891","DOI":"10.1145\/581888.581891"},{"key":"9","doi-asserted-by":"publisher","unstructured":"[9] J.D. Hiser and J.W. Davidson, \u201cEMBARC: An efficient memory bank assignment algorithm for retargetable compilers,\u201d ACM SIGPLAN Notices, vol.39, no.7, pp.182-191, 2004. 10.1145\/998300.997190","DOI":"10.1145\/998300.997190"},{"key":"10","unstructured":"[10] S. Steinke, L. Wehmeyer, B.-S. Lee, and P. Marwedel, \u201cAssigning program and data objects to scratchpad for energy reduction,\u201d Proc. 2002 Design, Automation and Test in Europe Conference and Exhibition, pp.409-415, 2002. 10.1109\/date.2002.998306"},{"key":"11","unstructured":"[11] W. Che, A. Panda, and K.S. Chatha, \u201cCompilation of stream programs for multicore processors that incorporate scratchpad memories,\u201d Proc. 2010 Design, Automation &amp; Test in Europe, DATE&apos;10, 3001 Leuven, Belgium, Belgium, pp.1118-1123, European Design and Automation Association, 2010. 10.1109\/date.2010.5456976"},{"key":"12","doi-asserted-by":"publisher","unstructured":"[12] Y. Guo, Q. Zhuge, J. Hu, J. Yi, M. Qiu, and E.H.-M. Sha, \u201cData placement and duplication for embedded multicore systems with scratch pad memory,\u201d IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.32, no.6, pp.809-817, June 2013. 10.1109\/tcad.2013.2238990","DOI":"10.1109\/TCAD.2013.2238990"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] S. Meftali, F. Gharsalli, F. Rousseau, and A.A. Jerraya, \u201cAn optimal memory allocation for application-specific multiprocessor system-on-chip,\u201d Proc. 14th International Symposium on System Synthesis, pp.19-24, ACM, 2001. 10.1145\/500001.500006","DOI":"10.1145\/500001.500006"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] F. Angiolini, L. Benini, and A. Caprara, \u201cPolynomial-time algorithm for on-chip scratchpad memory partitioning,\u201d Proc. 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp.318-326, ACM, 2003. 10.1145\/951710.951751","DOI":"10.1145\/951710.951751"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] M. Verma, L. Wehmeyer, and P. Marwedel, \u201cDynamic overlay of scratchpad memory for energy minimization,\u201d Proc. 2nd IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis, CODES+ISSS&apos;04, New York, NY, USA, pp.104-109, ACM, 2004. 10.1145\/1016720.1016748","DOI":"10.1145\/1016720.1016748"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] A. Yoshida, K. Koshizuka, and H. Kasahara, \u201cData-localization for Fortran macro-dataflow computation using partial static task assignment,\u201d Proc. 10th International Conference on Supercomputing, pp.61-68, ACM, 1996. 10.1145\/237578.237586","DOI":"10.1145\/237578.237586"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] K. Yamamoto, T. Shirakawa, Y. Oki, A. Yoshida, K. Kimura, and H. Kasahara, \u201cAutomatic local memory management for multicores having global address space,\u201d International Workshop on Languages and Compilers for Parallel Computing, LCPC 2016, Lecture Notes in Computer Science, vol.10136, pp.282-296, Springer, 2016. 10.1007\/978-3-319-52709-3_21","DOI":"10.1007\/978-3-319-52709-3_21"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] K. Kimura, M. Mase, H. Mikami, T. Miyamoto, J. Shirako, and H. Kasahara, \u201cOSCAR API for real-time low-power multicores and its performance on multicores and SMP servers,\u201d International Workshop on Languages and Compilers for Parallel Computing, LCPC 2009, Lecture Notes in Computer Science, vol.5898, pp.188-202, Springer, 2010. 10.1007\/978-3-642-13374-9_13","DOI":"10.1007\/978-3-642-13374-9_13"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] M. Ito, T. Hattori, Y. Yoshida, K. Hayase, T. Hayashi, O. Nishii, Y. Yasu, A. Hasegawa, M. Takada, M. Ito, H. Mizuno, K. Uchiyama, T. Odaka, J. Shirako, M. Mase, K. Kimura, and H. Kasahara, \u201cAn 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler,\u201d 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, pp.90-598, IEEE, 2008. 10.1109\/isscc.2008.4523071","DOI":"10.1109\/ISSCC.2008.4523071"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/3\/E103.C_2019LHP0010\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,7]],"date-time":"2020-03-07T03:20:52Z","timestamp":1583551252000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E103.C\/3\/E103.C_2019LHP0010\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,1]]},"references-count":19,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2020]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.2019lhp0010","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,3,1]]}}}