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Banerjee, \u201cSimultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era,\u201d Proceedings. 41st Design Automation Conference, 2004, pp.884-887, 2004. 10.1145\/996566.996801","DOI":"10.1145\/996566.996801"},{"key":"6","doi-asserted-by":"publisher","unstructured":"[6] J.T. Kao, M. Miyazaki, and A.R. Chandrakasan, \u201cA 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture,\u201d IEEE Journal of Solid-State Circuits, vol.37, no.11, pp.1545-1554, 2002. 10.1109\/jssc.2002.803957","DOI":"10.1109\/JSSC.2002.803957"},{"key":"7","doi-asserted-by":"publisher","unstructured":"[7] N. Mehta and B. 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